Power sequencing

The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation.

Power up sequence when DDR3L is used

1. O1V _DD , OV _DD , DV _DD , CV _DD , EV _DD , L1V _DD , LV _DD , TH_V _DD , USB_HV _DD , USB_OV _DD , AV _DD _CGA1, AV _DD _CGA2, AV _DD _PLAT, AV _DD _D1. Drive PROG_SFP = GND

a. PORESET_B should be driven asserted and held during this step.

2. V _DDC , V _DD , USB_SV _DD , S1V _DD

a. When Deep Sleep is not used, it is recommended to source V _DD and V _DDC from same power supply.

b. When Deep Sleep is used, V _DDC should ramp up before V _DD . Alternatively V _DD may ramp up together with V _DDC provided that the relative timing between V _DDC and V _DD ramp up conforms to Figure 9

3. G1V _DD , X1V _DD , AV _DD _SD1_PLL1, AV _DD _SD1_PLL2

a. All supplies in Step 3 may be sourced from same supply

Power up sequence when DDR4 is used

1. O1V _DD , OV _DD , DV _DD , CV _DD , EV _DD , L1V _DD , LV _DD , TH_V _DD , USB_HV _DD , USB_OV _DD , AV _DD _CGA1, AV _DD _CGA2, AV _DD _PLAT, AV _DD _D1, X1V _DD , AV _DD _SD1_PLL1, AV _DD _SD1_PLL2. Drive PROG_SFP = GND

a. PORESET_B should be driven asserted and held during this step.

2. V _DDC , V _DD , USB_SV _DD , S1V _DD

a. When Deep Sleep is not used, it is recommended to source V _DD and V _DDC from same power supply.

b. When Deep Sleep is used, V _DDC should ramp up before V _DD . Alternatively V _DD may ramp up together with V _DDC provided that the relative timing between V _DDC and V _DD ramp up conforms to Figure 9

3. G1V _DD

The supplies mentioned as OFF in "Status in Deep Sleep" column of Table 3 are switched ON while exit from Deep sleep power management mode. These supplies should also follow the same power up sequence as mentioned above.

Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs.

All supplies must be at their stable values within 75 ms.

Negate PORESET_B input when the required assertion/hold time has been met per Table 21.

NOTE

• EVT2_B may be unstable when PORESET_B is asserted.

The signal should not be used to enable switchable power supplies during this period.

• Ramp rate requirements should be met per Table 7 Warning

Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary.

This figure provides the V _DDC and V _DD ramp up diagram.

VDD

VDDC 10%

90%

10%

T1 <= 1 us T2 <= 1 us

Figure 9. V

_DDC

and V

_DD

ramp up diagram

For secure boot fuse programming, use the following steps:

1. After negation of PORESET_B, drive PROG_SFP = 1.8 V after a required minimum delay per Table 6.

2. After fuse programming is completed, it is required to return PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or powered down (V _DD ramp down) per the required timing specified in Table 6. See Security fuse processor, for additional details.

Warning

No activity other than that required for secure boot fuse programming is permitted while PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while PROG_SFP = GND.

This figure provides the PROG_SFP timing diagram.

PROG_SFP

V_DD

PORESET_B

90% OVDD

Fuse programming

tPROG_SFP_PROG

NOTE: PROG_SFP must be stable at 1.8 V prior to initiating fuse programming.

tPROG_SFP_DELAY

10% PROG_SFP

tPROG_SFP_RST

tPROG_SFP_VDD 10% PROG_SFP

90% VDD

90% OVDD

Figure 10. PROG_SFP timing diagram

This table provides information on the power-down and power-up sequence parameters for PROG_SFP.

Table 6. PROG_SFP timing

⁵

Driver type Min Max Unit Notes

tPROG_SFP_DELAY 100 - SYSCLKs 1

tPROG_SFP_PROG 0 - μs 2

tPROG_SFP_VDD 0 - μs 3

tPROG_SFP_RST 0 - μs 4

1. Delay required from the deassertion of PORESET_B to driving PROG_SFP ramp up. Delay measured from PORESET_B deassertion at 90% OV_DD to 10% PROG_SFP ramp up.

2. Delay required from fuse programming finished to PROG_SFP ramp down start. Fuse programming must complete while PROG_SFP is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while PROG_SFP driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while PROG_SFP = GND. After fuse programming is completed, it is required to return PROG_SFP = GND.

3. Delay required from PROG_SFP ramp down complete to V_DD ramp down start. PROG_SFP must be grounded to minimum 10% PROG_SFP before V_DD is at 90% V_DD.

4. Delay required from PROG_SFP ramp down complete to PORESET_B assertion. PROG_SFP must be grounded to minimum 10% PROG_SFP before PORESET_B assertion reaches 90% OVDD.

5. Only two secure boot fuse programming events are permitted per lifetime of a device.

In document T1040. Freescale Semiconductor. Data Sheet: Technical Data Rev. 2, 06/2015. Document Number T1040 (Page 53-56)

The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation.

Power up sequence when DDR3L is used

1. O1V DD , OV DD , DV DD , CV DD , EV DD , L1V DD , LV DD , TH_V DD , USB_HV DD , USB_OV DD , AV DD _CGA1, AV DD _CGA2, AV DD _PLAT, AV DD _D1. Drive PROG_SFP = GND

a. PORESET_B should be driven asserted and held during this step.

2. V DDC , V DD , USB_SV DD , S1V DD

a. When Deep Sleep is not used, it is recommended to source V DD and V DDC from same power supply.

b. When Deep Sleep is used, V DDC should ramp up before V DD . Alternatively V DD may ramp up together with V DDC provided that the relative timing between V DDC and V DD ramp up conforms to Figure 9

3. G1V DD , X1V DD , AV DD _SD1_PLL1, AV DD _SD1_PLL2

a. All supplies in Step 3 may be sourced from same supply

Power up sequence when DDR4 is used

1. O1V DD , OV DD , DV DD , CV DD , EV DD , L1V DD , LV DD , TH_V DD , USB_HV DD , USB_OV DD , AV DD _CGA1, AV DD _CGA2, AV DD _PLAT, AV DD _D1, X1V DD , AV DD _SD1_PLL1, AV DD _SD1_PLL2. Drive PROG_SFP = GND

a. PORESET_B should be driven asserted and held during this step.

2. V DDC , V DD , USB_SV DD , S1V DD

a. When Deep Sleep is not used, it is recommended to source V DD and V DDC from same power supply.

b. When Deep Sleep is used, V DDC should ramp up before V DD . Alternatively V DD may ramp up together with V DDC provided that the relative timing between V DDC and V DD ramp up conforms to Figure 9

3. G1V DD

The supplies mentioned as OFF in "Status in Deep Sleep" column of Table 3 are switched ON while exit from Deep sleep power management mode. These supplies should also follow the same power up sequence as mentioned above.

Items on the same line have no ordering requirement with respect to one another. Items on separate lines must be ordered sequentially such that voltage rails on a previous step must reach 90% of their value before the voltage rails on the current step reach 10% of theirs.

All supplies must be at their stable values within 75 ms.

Negate PORESET_B input when the required assertion/hold time has been met per Table 21.

NOTE

• EVT2_B may be unstable when PORESET_B is asserted.

The signal should not be used to enable switchable power supplies during this period.

• Ramp rate requirements should be met per Table 7 Warning

Only 300,000 POR cycles are permitted per lifetime of a device. Note that this value is based on design estimates and is preliminary.

This figure provides the V DDC and V DD ramp up diagram.

Figure 9. V

and V

ramp up diagram

For secure boot fuse programming, use the following steps:

1. After negation of PORESET_B, drive PROG_SFP = 1.8 V after a required minimum delay per Table 6.

2. After fuse programming is completed, it is required to return PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or powered down (V DD ramp down) per the required timing specified in Table 6. See Security fuse processor, for additional details.

Warning

No activity other than that required for secure boot fuse programming is permitted while PROG_SFP is driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may only occur while PROG_SFP = GND.

This figure provides the PROG_SFP timing diagram.

Figure 10. PROG_SFP timing diagram

This table provides information on the power-down and power-up sequence parameters for PROG_SFP.

Table 6. PROG_SFP timing

1. O1V _DD , OV _DD , DV _DD , CV _DD , EV _DD , L1V _DD , LV _DD , TH_V _DD , USB_HV _DD , USB_OV _DD , AV _DD _CGA1, AV _DD _CGA2, AV _DD _PLAT, AV _DD _D1. Drive PROG_SFP = GND

2. V _DDC , V _DD , USB_SV _DD , S1V _DD

a. When Deep Sleep is not used, it is recommended to source V _DD and V _DDC from same power supply.

b. When Deep Sleep is used, V _DDC should ramp up before V _DD . Alternatively V _DD may ramp up together with V _DDC provided that the relative timing between V _DDC and V _DD ramp up conforms to Figure 9

3. G1V _DD , X1V _DD , AV _DD _SD1_PLL1, AV _DD _SD1_PLL2

1. O1V _DD , OV _DD , DV _DD , CV _DD , EV _DD , L1V _DD , LV _DD , TH_V _DD , USB_HV _DD , USB_OV _DD , AV _DD _CGA1, AV _DD _CGA2, AV _DD _PLAT, AV _DD _D1, X1V _DD , AV _DD _SD1_PLL1, AV _DD _SD1_PLL2. Drive PROG_SFP = GND

2. V _DDC , V _DD , USB_SV _DD , S1V _DD

a. When Deep Sleep is not used, it is recommended to source V _DD and V _DDC from same power supply.

b. When Deep Sleep is used, V _DDC should ramp up before V _DD . Alternatively V _DD may ramp up together with V _DDC provided that the relative timing between V _DDC and V _DD ramp up conforms to Figure 9

3. G1V _DD

This figure provides the V _DDC and V _DD ramp up diagram.

2. After fuse programming is completed, it is required to return PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or powered down (V _DD ramp down) per the required timing specified in Table 6. See Security fuse processor, for additional details.