I2C interface

This section describes the DC and AC electrical characteristics for the I ² C interface.

3.18.1 I ² C DC electrical characteristics

This table provides the DC electrical characteristics for the I ² C interfaces operating at 3.3V.

Table 95. I

²

C DC electrical characteristics (DV

_DD

= 3.3V)

⁵

Parameter Symbol Min Max Unit Notes

Input high voltage V_IH 0.7 *

DVDD

- V 1

Table continues on the next page...

Table 95. I

²

C DC electrical characteristics (DV

_DD

= 3.3V)

⁵

(continued)

Parameter Symbol Min Max Unit Notes

Input low voltage V_IL - 0.2 *

DVDD

V 1

Output low voltage (I_OL = 3.0 mA)

VOL - 0.4 V

-Pulse width of spikes which must be suppressed by the input filter t_I2KHKL 0 50 ns 3 Input current each I/O pin (input voltage is between 0.1 x DVDD and 0.9

x DV_DD(max) II -50 50 µA 4

Capacitance for each I/O pin C_I - 10 pF

-Notes:

1. The min V_IL and max V_IH values are based on the respective min and max DV_IN values found in Table 3.

3. See the chip reference manual for information about the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if DV_DD is switched off.

5. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the I ² C interfaces operating at 2.5V.

Table 96. I

²

C DC electrical characteristics (DV

_DD

= 2.5V)

⁵

Parameter Symbol Min Max Unit Notes

Input high voltage V_IH 0.7 *

DVDD

- V 1

Input low voltage V_IL - 0.2 *

DVDD

V 1

Output low voltage (DV_DD = min, I_OL = 3 mA) V_OL 0 0.4 V

-Pulse width of spikes which must be suppressed by the input filter t_I2KHKL 0 50 ns 3 Input current each I/O pin (input voltage is between 0.1 x DV_DD and 0.9

x DV_DD(max)

I_I -50 50 µA 4

Capacitance for each I/O pin C_I - 10 pF

-Notes:

1. The min V_IL and max V_IH values are based on the respective min and max DV_IN values found in Table 3.

3. See the chip reference manual for information about the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if DV_DD is switched off.

5. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the I ² C interfaces operating at

1.8V.

Table 97. I

²

C DC electrical characteristics (DV

_DD

= 1.8V)

⁵

Parameter Symbol Min Max Unit Notes

Input high voltage V_IH 0.7 *

DVDD

- V 1

Input low voltage V_IL - 0.2 *

DVDD

V 1

Output low voltage (DV_DD = min, I_OL = 3 mA) V_OL 0 0.36 V

-Pulse width of spikes which must be suppressed by the input filter t_I2KHKL 0 50 ns 3 Input current each I/O pin (input voltage is between 0.1 x DV_DD and 0.9

x DV_DD(max)

I_I -50 50 µA 4

Capacitance for each I/O pin C_I - 10 pF

-Notes:

1. The min V_IL and max V_IH values are based on the respective min and max DV_IN values found in Table 3.

3. See the chip reference manual for information about the digital filter used.

4. I/O pins obstruct the SDA and SCL lines if DV_DD is switched off.

5. For recommended operating conditions, see Table 3.

3.18.2 I ² C AC timing specifications

This table provides the AC timing parameters for the I ² C interfaces.

Table 98. I

²

C AC timing specifications

⁵

Parameter Symbol¹ Min Max Unit Notes

SCL clock frequency f_I2C 0 400 kHz 2

Low period of the SCL clock t_I2CL 1.3 - μs

-High period of the SCL clock tI2CH 0.6 - μs

-Setup time for a repeated START condition t_I2SVKH 0.6 - μs

-Hold time (repeated) START condition (after this period, the first clock pulse is generated)

t_I2SXKL 0.6 - μs

-Data setup time t_I2DVKH 100 - ns

-Data input hold time: t_I2DXKL μs 3

CBUS compatible masters I²C bus devices

-0

-Data output delay time t_I2OVKL - 0.9 μs 4

Setup time for STOP condition t_I2PVKH 0.6 - μs

-Bus free time between a STOP and START condition t_I2KHDX 1.3 - μs

-Noise margin at the LOW level for each connected device

(including hysteresis) V_NL 0.1 x OV_DD - V

-Noise margin at the HIGH level for each connected device

(including hysteresis) V_NH 0.2 x OV_DD - V

-Table continues on the next page...

Table 98. I

²

C AC timing specifications

⁵

(continued)

Parameter Symbol¹ Min Max Unit Notes

Capacitive load for each bus line Cb - 400 pF

-Notes:

1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t_I2DVKH symbolizes I²C timing (I2) with respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. Also, t_I2SXKL symbolizes I²C timing (I2) for the time that the data with respect to the START condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I²C timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the t_I2C clock reference (K) going to the high (H) state or setup time.

2. The requirements for I²C frequency calculation must be followed. See Determining the I²C Frequency Divider Ratio for SCL (AN2919).

3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP condition. When the chip acts as the I²C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the chip as transmitter, see Determining the I²C Frequency Divider Ratio for SCL (AN2919).

4. The maximum t_I2OVKL has to be met only if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

5. For recommended operating conditions, see Table 3.

This figure provides the AC test load for the I ² C.

Output Z0= 50 Ω

RL = 50 Ω

DVDD/2

Figure 57. I

²

C AC test load

This figure shows the AC timing diagram for the I ² C bus.

SDA

SCL

S Sr P S

tI2KHDX

tI2PVKH

tI2KHKL

tI2SVKH

tI2SXKL

tI2CH

tI2DVKH

tI2DXKL, tI2OVKL

tI2CL

tI2SXKL

Figure 58. I

²

C Bus AC timing diagram

In document T1040. Freescale Semiconductor. Data Sheet: Technical Data Rev. 2, 06/2015. Document Number T1040 (Page 129-133)