PART D: ARMV8 EXTERNAL DEBUG
8 DEBUG STATE
8.4 Behavior in Debug state
8.4.2 Executing instructions in Debug state
Rationale: see Behavior of instructions executed in Debug state on page 265.
The instructions executed in Debug state must be either T32 or A64 instructions, depending on the current execution state.
All T32 instructions are treated as unconditional, regardless of PSTATE.IT. See Process state (PSTATE) in Debug state above.
Each instruction falls into one of these groups:
Debug state instructions (instructions that are changed in Debug state)
Instructions that are unchanged in Debug state.
Instructions that are unpredictable in Debug state.
If EDSCR.SDD == 1 then no instruction executed in Non-secure state can cause entry into Secure state. See Security in Debug state on page 153.
Debug state instructions (instructions that are changed in Debug state)
The A64 and T32 instructions defined in Debug state instructions on page 154 are allowed in Debug state but UNDEFINED in Non-debug state:
DCPS
DPRS, decoded from ERET in T32
System instructions for accessing DLR_EL0 and DSPSR_EL0.
A64 instruction set (Figure 58) T32 instruction set (32-bit encodings) (Figure 59) Debug state instructions
These instructions are UNDEFINED in Non-debug state.
Note: DCPS can be UNDEFINED in certain conditions in Debug state. See DCPS on page 154.
DCPS DCPS
DRPS ERET, decoded as DRPS
(MRS|MSR) (DLR_EL0|DSPSR_EL0) (MRC|MCR) (DLR|DSPSR)
Table 50: Instructions that are changed in Debug state
Instructions that are unchanged in Debug state
Any T32 instruction that uses PC or APSR_nzcv as a source or destination register is excluded from this table. Only 32-bit T32 encodings are included in this table.
A64 instruction set (Figure 60) T32 instruction set (32-bit encodings) (Figure 61) Any instruction that is UNDEFINED in Non-debug state
Excluding:
Any instruction listed in Debug state instructions (instructions that are changed in Debug state)
Any instruction listed in Instructions that are UNPREDICTABLE in Debug state that is UNDEFINED due to a configurable trap, enable or disable that is not defined to be RES0 or RES1.
Instructions that move system or special registers to/from general-purpose registers
Includes the instructions to transfer a general-purpose register to/from the DTR.
Excludes PSTATE access instructions in AArch64 state and CPSR access instructions in AArch32 state.
Excludes instructions for accessing banked registers for the current mode in AArch32 state.
(MRS|MSR) <special_reg>, other than NZCV, DAIF, DAIFSet, DAIFClr, SPSel and CurrentEL
(MRS|MSR) <spec_reg>_<mode>, other than cases where are UNPREDICTABLE in Non-debug state
(MRS|MSR) <system_reg> (MRS|MSR) SPSR
(MRC|MCR) <system_reg>, including all CP15 and CP14 system registers, other than MRC to APSR_nzcv (VMRS|VMSR) <vfp_system_reg>, other than VMRS to APSR_nzcv
Floating-point moves between a SIMD&FP register and a general-purpose register FMOV (between general register and single precision
register)
VMOV (between general-purpose register and single precision register)
FMOV (between general register and double precision register)
VMOV (between two general-purpose registers and doubleword floating-point register)
FMOV (between general register and a SIMD element)
SIMD moves between a SIMD&FP register and a general-purpose register
INS (from general register to SIMD element) VMOV (between general-purpose register and scalar) UMOV (from SIMD element to general register)
Barrier instructions
ISB, DSB, DMB ISB, DSB, DMB
A64 instruction set (Figure 60) T32 instruction set (32-bit encodings) (Figure 61) Memory access instructions at various access sizes
With the following constraints in AArch64:
General-purpose registers only
One of the following addressing modes:
— Unscaled (9-bit signed) immediate offset
— Immediate (9-bit signed) post-indexed
— Immediate (9-bit signed) pre-indexed
— Unprivileged (9-bit signed)
Not literal
— Acquire/release exclusive pair
32-bit and 64-bit target register variants
With the following constraints in AArch32:
General-purpose registers only
One of the following addressing modes:
— Immediate (8-bit or 12-bit) offset
— Immediate (8-bit) post-indexed
— Immediate (8-bit) pre-indexed
— Unprivileged (8-bit)
— Acquire/release exclusive doubleword LD{U|T}R{B|H|SB|SH|SW} (immediate, not literal) LDR{B|H|SB|SH}{T}.W, LDRD (immediate, not literal)
ST{U|T}R{B|H}(immediate) STR{B|H}{T}.W, STRD (immediate)
LD(A|X|AX)R{B|H}, ST(L|X|LX)R{B|H} LD(REX|A|AEX){B|H}, ST(REX|L|LEX){B|H}
LD{A}XP, ST{L}XP LD(R|A)EXD, ST(R|L)EXD
Move to general-purpose register With the following constraints in AArch64:
Wide immediate constants
Between the stack pointer and a general register
With the following constraints in AArch32:
Wide immediate constants
MOVZ, MOVN, MOVK (immediate) MOVW, MOVT (immediate) MOV (between general register and stack pointer)
Cache maintenance, Send Event, NOP and Clear Exclusive
IC, DC, TLBI, AT IC*, DC*, BPI*, TLBI* and AT* CP15 operations, other
than those which are deprecated for ARMv8
SEV, SEVL SEV.W, SEVL.W
NOP (no-operation hint) NOP.W (no-operation hint)
CLREX CLREX
Table 51: Instructions that are unchanged in Debug state
Instructions that are UNPREDICTABLE in Debug state This section describes all instructions not listed in either:
Debug state instructions (instructions that are changed in Debug state).
Instructions that are unchanged in Debug state.
These instructions are CONSTRAINEDUNPREDICTABLE in Debug state. In general permissible the behaviors are:
Generate an Undefined Instruction exception.
Execute as a NOP
If the instruction reads the PC or PSTATE, use an UNKNOWN value.
If the instruction modifies the PC or PSTATE (other than by advancing PC to the sequentially next instruction), set DSPSR_EL0 and DLR_EL0 to UNKNOWN values.
If the instruction is similar to a Debug state instruction, execute as that Debug state instruction.
Have the same behavior as in Non-debug state.
The numbered lists in Table 52 give the permissible behaviors for each set of instructions. If an instruction appears in multiple locations, the permissible behaviors is the union of those listed.
A64 instruction set T32 instruction set Exception generating instructions
1. Are UNDEFINED. 2. Are a NOP.
3. For SVC, HVC, and SMC, have the behavior of DCPS<n>, where <n> is a 1, 2 or 3 respectively.
4. Executes as in Non-debug state by generating the exception the instruction would generate in Non-debug state. The exception is taken as described in Exceptions in Debug state on page 156, except that SMC must not generate a Secure Monitor Call exception from Non-secure state if EDSCR.SDD is set to 1.
SVC, HVC, SMC, BRK, HLT SVC, HVC, SMC, UDF, BKPT, HLT
Instructions that explicitly write to the PC (branches) 1. Are UNDEFINED.
2. Are a NOP.
3. Executes as in Non-debug state without branching and setting DSPSR_EL0 and DLR_EL0 to UNKNOWN values.
B, B.cond, BL, BLR, BR, CB{N}Z, RET, TB{N}Z B, B (conditional), CB{N}Z, BL, BX, BLX (register or immediate), BXJ, TB(B|H)
MOV pc, and related instructions
LDR pc, LDM {...,pc}, POP {...,pc}
Exception return and related instructions 1. Are UNDEFINED.
2. Are a NOP.
3. Execute as in Non-debug state without branching, setting DSPSR_EL0 and DLR_EL0 to UNKNOWN values, and either:
— Behaving as DRPS in place of the exception return part of the instruction, using an UNKNOWN SPSR value.
— Not changing Exception level or AArch32 processor mode.
Note: The T32 ERET instruction is decoded as DRPS and not included in this list.
ERET SRS, RFE, SUBS pc,lr and related instructions
Instructions that attempt to alter the operating state of the processor, other than DCPS and DRPS 1. Are UNDEFINED.
2. Are a NOP.
3. Execute as in Non-debug state, setting DSPSR_EL0 and DLR_EL0 to UNKNOWN values.
MSR (DAIFSet,DAIFClr|SPSel) (immediate) CPS{IE|ID}, SETEND, IT
MSR (NZCV|DAIF|SPSel) (register) MSR (APSR|CPSR) (register or immediate) Instructions that request entry to a low-power state
1. Are UNDEFINED. 2. Are a NOP.
3. Generate a Trap exception if the corresponding instruction would be trapped in Non-debug state.
Note: This means these instructions do not request entry to a low-power state when executed in Debug state.
WFE, WFI WFE, WFI
Instructions that read the PC 1. Are UNDEFINED.
2. Are a NOP.
3. Execute as in Non-debug state, using an UNKNOWN value for the PC operand.
LDR{SW} (literal) LDR{B|H|SB|SH} (literal)
ADR{P} ADR{L|H}
PRFM (literal) PLD (literal), PLI (literal)
Instructions that read the NZCV condition flags or other PSTATE fields
A64 instruction set T32 instruction set 1. Are UNDEFINED.
2. Are a NOP.
3. Execute as in Non-debug state:
— For the conditional operations and those taking PSTATE.C as an input, using UNKNOWN values for the condition flags.
— For the MRS operations, using an UNKNOWN value for the special purpose register.
CSEL, CSINC, CSINV, CSNEG, CCMN, CCMP, FCSEL, FCCMP{E}
SEL, VSEL
ADC{S}, SBC{S} ADC, SBC, all instructions with an RRX shift
MRS (NZCV|DAIF|SPSel|CurrentEL) MRS CPSR
Instructions that explicitly modify the NZCV condition, Q, or GE flags 1. Are UNDEFINED.
2. Are a NOP.
3. Execute as in Non-debug state, setting DSPSR_EL0 and DLR_EL0 to UNKNOWN values.
ADDS, SUBS, ADCS, SBCS, ANDS, BICS, CCMN, CCMP CMP, TST, TEQ, CMN
FCMP{E}, FCCMP{E} <opc>S
MSR NZCV (register) MSR (APSR|CPSR) (register or immediate)
MRC p14,0,APSR_nzcv,c0,c1,0 (DBGDSCRint) VMRS APSR_nzcv,FPSCR
Q{D}ADD, Q{D}SUB, SMLA(B|T)(B|T), SMLAD, SMLAW(B|T), SMLSD, SMUAD
(S|U)SAT{16}, (S|U)ADD(8|16), (S|U)ASX, (S|U)SAX, (S|U)SUB(8|16)
All other instructions 1. Are UNDEFINED. 2. Are a NOP.
3. Execute as in Non-debug state.
Note:
This includes instructions defined as UNPREDICTABLE in Non-debug state. These instructions are UNPREDICTABLE in Debug state. This includes some T32 instructions which specify R15 as a destination or source register, such as:
MOV.W R15, #<uimm16>
LDREX R15, [Rn]
[AArch32UNP] describes the CONSTRAINED UNPREDICTABLE behaviors for these instructions. In Debug state these
CONSTRAINED UNPREDICTABLE choices are further restricted:
Instructions that specify R15 as a destination:
— Are not permitted to branch, as the architecture does not define a branch operation in Debug state.
— Might set DLR_EL0 and DSPSR_EL0 to UNKNOWN values.
— Might have any of the other permitted behaviors.
Instructions that specify R15 as a source operand:
— Cannot use PC+offset, as there is no architecturally-defined PC in Debug state.
— Might have any of the other permitted behaviors, including using an UNKNOWN value Table 52: Instructions that are UNPREDICTABLE in Debug state