Synchronization of changes to external debug registers

This section describes the synchronization requirements for the external debug interface.

For more information on how these requirements affect debug, see:

 Synchronization and Software debug events on page 51.

 Synchronization and Halting debug events on page 137.

 Synchronization of DCC and ITR accesses on page 168.

 Synchronization and the authentication interface on page 237.

In this section, accesses from the external debug interface are referred to as external reads and external writes. Accesses to system registers are referred to as direct reads, direct writes, indirect reads and indirect writes.

Note: Direct read, direct write, indirect read and indirect write are defined by [v8Exception]. [v8Exception]

classifies external reads as indirect reads and external writes as indirect writes.

Writes to the same register are serialized, meaning they are observed in the same order by all observers, although some observers might not observe all of the writes. With the exception of the registers listed below, external writes to different registers are not necessarily observed in the same order by all observers as the order that they complete.

Synchronization of DCC and ITR accesses on page 168 describes the synchronization requirements for the DCC and ITR.

Changes to the IMPLEMENTATION DEFINED authentication interface are external writes to the authentication status registers by the master of the authentication interface. See Synchronization and the authentication interface on page 237.

Explicit synchronization is not required for an external read or external write by an external agent to be observable to a following external read or external write by that agent to the same register using the same address, and so is never required for registers that are accessible only in the external debug interface.

A change to a register in the External Debug reset domain caused by an External Debug reset is guaranteed to be observable to indirect reads from the Core power domain only following a Cold reset of the Core power domain. This might be a Cold reset that is coincident with the External Debug reset.

Note: These registers are EDECR.{SS,RCE,OUCE} and multi-cycle CTI output trigger events.

Otherwise, explicit synchronization is normally required following an external write to any register, for that write to be observable by a direct access, indirectly read by an instruction, or an external read of the register using a different address. Some registers are guaranteed to be observable to all observers in finite time without explicit synchronization. For more information, see [v8Exception].

This means that an external write by an external debugger (the host) is guaranteed to have an effect on subsequent instructions executed by the processor, only if all of the following are true:

 the host can guarantee that that write has completed

 the processor has executed a context synchronization operation (CSO)

 there is a guarantee that the CSO was executed after the write had completed.

The order and synchronization of direct reads and direct writes of system registers is defined by [v8Exception]. The host can guarantee completion of a write by, for example:

 marking the memory as Device-nGnRnE and executing a DSB barrier, if this is a supported property of the system

 reading back the value written

 some guaranteed property of the connection between processor and host.

Note: For an external Debug Access Port (DAP) this is an IMPLEMENTATION DEFINED property. For a CoreSight system using APB-AP to access a debug APB, a write is guaranteed to complete before the APB-AP allows a second APB transaction to complete.

The host and processor can guarantee ordering by, for example, message passing in some way that is ordered with respect to the external write and the CSO, in the normal ways for which the memory ordering model provides such ordering guarantees.

External reads and external writes complete in the order which they arrive at the processor. For accesses to different register locations the host must create this order by, for example:

 marking the memory as Device-nGnRnE or Device-nGnRE

 use of appropriate memory barriers

 some guaranteed property of the connection between processor and host.

Note: For an external DAP this is an IMPLEMENTATION DEFINED property. For a CoreSight system using APB-AP to access a debug APB, accesses complete in order.

However, the host cannot force synchronization of completed writes without halting the processor. Executing an ISB instruction (both in Non-debug state and in Debug state) and exiting from Debug state will force synchronization. If the processor is in Debug state, executing an ISB instruction is guaranteed to explicitly synchronize any external reads, external writes, and changes the authentication interface that are ordered before the external write to EDITR.

For any given observer, external writes to the following register groups are guaranteed observable in the same order in which they complete:

 the breakpoint registers, DBGBCRn_EL1, DBGBVRn_EL1[63:32] and DBGBVRn_EL1[31:0]

 the watchpoint registers, DBGWCRn_EL1, DBGWVRn_EL1[63:32] and DBGWVRn_EL1[31:0].

This guarantee only applies to external writes to registers within one of these groups. There is no guarantee of ordering of synchronization of external writes with respect to external writes to other registers (for example, EDSCR) or between breakpoints and watchpoints, including watchpoints linked to Context breakpoints.

Note: This means that a debugger can rely on the external writes being synchronized in the same order that they complete. It does not mean that a debugger can rely on the external writes being synchronized in finite time.

In the simple sequential execution an indirect write that occurs as the side-effect of an access happens atomically with and immediately after the access, meaning no other accesses allowed between the register access and its side effect.

If a register is accessed simultaneously by two (or more) interfaces, the behavior must be as if the accesses occurred atomically in any order, as in the examples below.

Registers such as the DBGCLAIM tag registers have the property for certain bits that writing zero is ignored whereas writing one has an action. This means that simultaneous writes must be merged rather than simply prioritized.

Registers with that property that support both external debug and system register access include DBGCLAIMSET_EL1, DBGCLAIMCLR_EL1, PMCR_EL0.{C,P}, PMOVSSET_EL0, PMOVSCLR_EL0, PMCNTENSET_EL0, PMCNTENCLR_EL0, PMINTENSET_EL1, PMINTENCLR_EL1, and PMSWINC_EL0 (OPTIONAL and deprecated).

16.3.1 Examples of synchronization of changes to external debug registers

Example 1: Order of synchronization of breakpoint/watchpoint register writes

Initially DBGBVR0_EL1[63:0] == 0x8000 and DBGBCR0_EL1 == 0x0181, meaning a breakpoint is enabled on the halfword (T32) instruction at address 0x8000.

A sequence of external writes occur in the following order:

a. 0x0000 is written to DBGBCR0_EL1, disabling breakpoint 0.

b. 0x9000 is written to DBGBVR0_EL1[31:0].

c. 0x0061 is written to DBGBCR0_EL1, enabling a breakpoint on the halfword at address 0x9002.

The external writes must be synchronized and hence be observable to indirect reads in the same order as the external writes complete, meaning that at no point is there a breakpoint enabled on either of the halfwords at address 0x8002 and 0x9000.

Similarly a breakpoint or watchpoint must be disabled:

 if both halves of a 64-bit address have to be updated

 if any of the DBGBCRn_EL1 or DBGWCRn_EL1 fields are modified at the same time as updating the address.

Example 2: Simultaneous accesses to DTR registers Initially EDSCR.{TXfull, TXU, ERR} are 0, and then, at the same time:

a. 0x0DCCDA7A is written to DBGDTRTX_EL0 by a system register write b. DBGDTRTX_EL0 is read by an external debug interface read.

The following results are permitted:

(a) followed by (b)

 EDSCR.TXfull is zero, cleared by (b)

 EDSCR.{TXU, ERR} are both 0

 the external debug interface read returns 0x0DCCDA7A. (b) followed by (a)

 EDSCR.{TXU, ERR} are both 1, as (b) caused an underrun

 the external debug interface returned an UNKNOWN value

 EDSCR.TXfull is 1, set by (a)

 DTRTX has the value 0x0DCCDA7A, set by (a).

Example 3: Simultaneous writes to CLAIM registers Initially all CLAIM tag bits are clear, and then, at the same time:

a. 0x01 is written to DBGCLAIMSET_EL1 by a direct write, followed by an explicit context synchronization operation.

b. 0x02 is written to DBGCLAIMSET_EL1 by an external write.

If immediately following:

c. DBGCLAIMCLR_EL1 is read by a direct read d. DBGCLAIMCLR_EL1 is read by an external read.

Then the direct read can return either 0x01 or 0x03, and the external read can return either 0x02 or 0x03. The only permitted final result for the CLAIM tags is the value 0x03, as this would be the result for both (a) followed by (b) and (b) followed by (a), as the external write is guaranteed to be observable to a direct read in finite time (see [v8Exception]).

It is not possible that the direct read returns 0x01 and the external read returns 0x02, as the writes to DBGCLAIMCLR_EL1 are serialized.

Assuming both observers observe the value 0x03, and then, at the same time:

e. 0x04 is written to DBGCLAIMSET_EL1 by a direct write, followed by an explicit context synchronization operation

f. 0x01 is written to DBGCLAIMCLR_EL1 by an external write.

The only permitted final result for the CLAIM tags is the value 0x06. Example 4: External debug reset of EDECR

An external debugger has set EDECR.OUCE = 1. Later, an External Debug reset clears this bit to 0:

a. The External Debug reset was not coincident with a Cold reset. It is CONSTRAINED UNPREDICTABLE whether a following OS Unlock event:

— Observes the previous value of EDECR.OUCE and generates an OS Unlock Catch debug event, even if there has been a context synchronization operation since the External debug reset.

— Observes the reset value of EDECR.OUCE and does not generate a debug event

b. The External Debug reset was coincident with a Cold reset. A following OS Unlock event will observe the reset value of EDECR.OUCE and not generate a debug event.

An external debugger has set EDECR.RCE = 1. Later, an External Debug reset clears this bit to 0. The External Debug reset was not coincident with a Cold reset. It is CONSTRAINED UNPREDICTABLE whether a following Warm reset will observe the reset value of EDECR.RCE. However, a following Cold reset will observe the reset value of EDECR.RCE and not generate a debug event.