5.9 Self-hosted debug system register definitions
5.9.6 Monitor Debug System Control Register, MDSCR_EL1
in AArch64 state, accessed as a 32-bit read/write system register
in AArch32 state, accessed as a 32-bit read/write CP14 register with some read-only fields, the Debug Status and Control Register, DBGDSCRext
used exclusively by self-hosted debug
has modified behavior on reads and writes that depends on OSLSR_EL1.OSLK (the OS lock), see When OSLSR_EL1.OSLK == 1 (the OS lock is locked) below.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTdis 0 0 0 (0) (0) (0) (0) SS
RXfull TXfull RXO TXU TDA HDE TDCC ERR
X = bit is read-only MDE KDE
(0) = See [v8Exception] for how RES0 applies to these bits / = bit is read-only when the OS lock is unlocked, read/write when the OS lock is locked
Figure 19: MDSCR_EL1 (AArch64) bit assignment
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTdis NS (0) MOE (0)
RXfull TXfull RXO TXU TDA SPNIDdis HDE UDCCdis (TDCC) ERR X = bit is read-only SPIDdis MDBGen (MDE)
(0) = See [v8Exception] for how RES0 applies to these bits / = bit is read-only when the OS lock is unlocked, read/write when the OS lock is locked
Figure 20: DBGDSCRext (AArch32) bit assignment Bits [31,28,25:24,20:19,11:7,1]
Reserved, RES0. RXfull, TXfull, bits [30:29]
DCC status flags, for save/restore. When OSLSR_EL1.OSLK == 0 (OS lock is unlocked): These bits are read-only.
In AArch64 state, software must treat them as UNKNOWN and use an SBZP policy for writes. In AArch32 state, ARM deprecates use of these bits. This means software should treat them
as UNKNOWN and use an SBZP policy for writes.
See also When OSLSR_EL1.OSLK == 1 (the OS lock is locked) below. Bits [27:26,23:21,14,6]
Save/restore bits. These bits are defined by When OSLSR_EL1.OSLK == 1 (the OS lock is locked) below: When OSLSR_EL1.OSLK == 0 (OS lock is unlocked):
these bits are read-only
software must treat them as UNKNOWN and use an SBZP policy for writes.
Note: In v7 Debug, DBGDSCRext[14], HDBGen, is read/write, but forced to RAZ when DBGEN is LOW. In v7.1 Debug it is UNKNOWN and WI when not doing save/restore. In v8-A, it is unaffected by DBGEN.
Bits [18:16], when accessed as MDSCR_EL1 in AArch64 state
Reserved. Must be implemented as RAZ/WI. Software must not rely on this property as the behavior of reserved values might change in a future revision of the architecture.
NS, bits [18], when accessed as DBGDSCRext in AArch32 state
Non-secure status. Returns the inverse of IsSecure(). ARM deprecates use of this field. SPNIDdis, bit [17], when accessed as DBGDSCRext in AArch32 state
Secure privileged profiling disabled status bit. Reflects the value of
ProfilingProhibited(TRUE,EL1). Permitted values are:
0 Profiling allowed in Secure privileged modes. 1 Profiling prohibited in Secure privileged modes.
See Performance Monitors and security on page 97. ARM deprecates use of this field. SPIDdis, bit [16], when accessed as DBGDSCRext in AArch32 state
Secure privileged AArch32 invasive self-hosted debug disabled status bit. Returns the inverse of
DebugSPD32(). Permitted values are:
0 Self-hosted debug enabled in Secure privileged AArch32 modes. 1 Self-hosted debug disabled in Secure privileged AArch32 modes.
See Enabling debug exceptions other than Software Breakpoint Instruction routed to an EL using AArch32 on page 54. ARM deprecates use of this field.
MDE, bit [15], when accessed as MDSCR_EL1 in AArch64 state MDBGen, bit [15], when accessed as DBGDSCRext in AArch32 state
Monitor debug events. Enables Breakpoint, Watchpoint and Vector Catch exceptions. Permitted values are:
0 Breakpoint, Watchpoint and Vector Catch exceptions disabled. 1 Breakpoint, Watchpoint and Vector Catch exceptions enabled. Notes:
— Unlike v7-A, DBGDSCRext.MDBGen is not forced to RAZ when DBGEN is LOW, consistent with the separation of external debug enable and self-hosted debug enable.
— Breakpoint and Watchpoint debug events are also enabled by EDSCR.HDE. See Part D: ARMv8 External Debug.
KDE, bit [13], when accessed as MDSCR_EL1 in AArch64 state
Local (“kernel”) debug enable. If the debug exception target EL is using AArch64, enables debug exceptions from within the debug exception target EL. Permitted values are:
0 Debug exceptions other than Software Breakpoint Instruction exceptions disabled within the debug exception target EL.
1 Debug exceptions enabled within the debug exception target EL. RES0 if the debug exception target EL is using AArch32.
Bit [13], when accessed as DBGDSCRext in AArch32 state
Reserved, RES0. See [v8Exception] for details of how RES0 applies to this bit. TDCC, bit [12], when accessed as MDSCR_EL1 in AArch64 state
UDCCdis, bit [12] when accessed as DBGDSCRext in AArch32 state
Trap accesses to the debug comms channel in EL0. See Accessing debug system registers on page 63.
Bits [5:2], when accessed as MDSCR_EL1 in AArch64 state
Reserved, RES0. See [v8Exception] for details of how RES0 applies to these bits. MOE, bits [5:2], when accessed as DBGDSCRext in AArch32 state
Method of Entry syndrome bits. See Effect of taking debug exception to an EL using AArch32 on system registers on page 59.
SS, bit [0], when accessed as MDSCR_EL1 in AArch64 state
Software Step control bit. If the debug exception target EL is using AArch64, enables Software Step exceptions. Permitted values are:
0 Software Step disabled 1 Software Step enabled.
For full details of the operation of the MDSCR_EL1.SS bit, see Software Step debug event on page 39. RES0 if the debug exception target EL is using AArch32.
Bit [0], when accessed as DBGDSCRext in AArch32 state
Reserved, RES0. See [v8Exception] for details of how RES0 applies to this bit.
When OSLSR_EL1.OSLK == 1 (the OS lock is locked)
When the OS lock is locked, MDSCR_EL1 is part of the software save/restore mechanism for external debug. It provides a mechanism for an operating system to access some fields of EDSCR that are otherwise read- only or not visible to software, so it can save/restore these settings over a power-down on behalf of the external debugger.
These bits are read/write when the OS lock is locked, reads and writes must access the EDSCR field, but software must treat this as an UNKNOWN value that it preserves over the save/restore sequence.
See also Multiple views of Debug Control and Status Registers below.
Multiple views of Debug Control and Status Registers
The debug architecture provides multiple registers that provide views onto common pieces of debug control registers and status flags:
in AArch64 state, the MDCCSR_EL0 and MDSCR_EL1 system registers in AArch32 state, the DBGDSCRint and DBGDSCRext CP14 registers by the external debug interface, the EDSCR external debug register.
Each of these common registers has a “physical” location in the architecture, and treats the other views as aliases. Table 29 summarizes this aliasing, and gives the access permissions for each of the bits in the Debug System Control Registers. For definitions of each system register bit, see:
The definitions above, for bits [18:15,13:12,5:2,0].
External Debug Status and Control Register, EDSCR on page 203, for bits [30:29,27:26,23:21,14,6]. All other bits are reserved, RES0. Table 29 gives the implementation requirements, but software must not rely on reserved fields being RAZ or RAZ/WI.
Bits
Physical register or status value for system register views EDSCR MDCCSR_EL0 / DBGDSCRint (read-only) MDSCR_EL1 / DBGDSCRext OSLK == 0 OSLK == 1
AArch64 AArch32 AArch64 AArch32 AArch64 AArch32
[31] Reserved RAZ/WI RAZ RAZ/WI RAZ/WI
[30] EDSCR.RXfull RO RO ROa ROb R/W R/W
[29] EDSCR.TXfull RO RO ROa ROb R/W R/W
[28] Reserved (ITO)c RAZ RAZ/WI RAZ/WI
[27] EDSCR.RXO RO RAZ ROa R/Wd
[26] EDSCR.TXU RO RAZ ROa R/Wd
[25] Reserved (PipeAdv)c RAZ RAZ/WI RAZ/WI
[24] Reserved (ITE)c RAZ RAZ/WI RAZ/WI
[23:22] EDSCR.INTdis R/W RAZ ROa R/Wd
[21] EDSCR.TDA R/W RAZ ROa R/Wd
[20] Reserved (MA)c RAZ RAZ/WI RAZ/WI
[19] Reserved RAZ/WI RAZ RAZ/WI RAZ/WI
[18] !IsSecure() RO RAZ ROb,e RAZ/WI ROb RAZ/WI ROb
[17] ProfilingProhibited(TRUE,EL1) RAZ/WI RAZ ROb,e RAZ/WI ROb RAZ/WI ROb
[16] !DebugSPD32() (SDD)c RAZ ROb,e RAZ/WI ROb RAZ/WI ROb
[15] MDSCR_EL1.MDE RAZ/WI RAZ ROe R/W R/W
[14] EDSCR.HDE R/W RAZ ROa R/Wd
[13] MDSCR_EL1.KDE (RW[3])c RAZ R/W RES0f R/W RES0f
[12] MDSCR_EL1.TDCC (RW[2])c RAZ ROb,e R/W R/W
[11:10] Reserved (RW[1:0])c RAZ RAZ/WI RAZ/WI
Bits
Physical register or status value for system register views EDSCR MDCCSR_EL0 / DBGDSCRint (read-only) MDSCR_EL1 / DBGDSCRext OSLK == 0 OSLK == 1
AArch64 AArch32 AArch64 AArch32 AArch64 AArch32
[7] Reserved (A)c RAZ RAZ/WI RAZ/WI
[6] EDSCR.ERR RO RAZ ROa R/Wd
[5:2] DBGDSCRext.MOE (STATUS[5:2])c RAZ ROe RES0f R/W RES0f R/W
[1] Reserved (STATUS[1])c RAZ RAZ/WI RAZ/WI
[0] MDSCR_EL1.SS (STATUS[0])c RAZ R/W RES0f R/W RES0f
a. Software must not rely on this bit ignoring writes when OSLK==0, and must treat the value read as UNKNOWN. b. ARM deprecates use of this field.
c. This field does not map to a system register view. See External Debug Status and Control Register, EDSCR on page 203. d. Software must treat this value as an UNKNOWN value on save that should be preserved on restore.
e. UNKNOWN at EL0.
f. See [v8Exception] for details of how RES0 applies to this bit.
Table 29: Implementation requirements for Debug System Control Registers