PART C: PERFORMANCE MONITORS EXTENSION
6 PERFORMANCE MONITORS
6.7 Performance Monitors registers
6.7.1 Performance Monitors system register map
The system register map is updated from that in [v7A] to use op1 as described in [v8Exception] and add direct access to Performance Monitors counters.
CRn CRm op2 op1a
Access Description / see 32 64
c9 c12 0 0 3 R/W Performance Monitors Control Register, PMCR_EL0 on page 106 1 0 3 R/W PMCNTENSET_EL0 Count Enable Set and Clear Registers,
PMCNTENSET_EL0 and
PMCNTENCLR_EL0 on page 113
2 0 3 R/W PMCNTENCLR_EL0
3 0 3 R/W PMOVSCLR_EL0b, Overflow Flag Status Set and Clear Registers, PMOVSSET_EL0 and PMOVSCLR_EL0 on page 114
4 0 3 WO Software Increment Register, PMSWINC_EL0 on page 115 5 0 3 RW Event Counter Selection Register, PMSELR_EL0, see [v7A]
6 0 3 RO PMCEID0_EL0 Common Event Identification registers,
PMCEID0_EL0 and PMCEID1_EL0 on page 115
7 0 3 RO PMCEID1_EL0
c13 0 0 3 RW Performance Monitors Cycle Counter, PMCCNTR_EL0 on page 108 1 0 3 RW Selected Event Type and Filter Register, PMXEVTYPER_EL0 on
page 109
2 0 3 RW Selected Event Counter Register, PMXEVCNTR_EL0 on page 109 c14 0 0 3 RO/RWc User Enable Register, PMUSERENR_EL0 on page 112
1 0 0 RW PMINTENSET_EL1 Interrupt Enable Set and Clear Registers, PMINTENSET_EL1 and PMINTENCLR_EL1 on page 113
2 0 0 RW PMINTENCLR_EL1
3 0 3 RW PMOVSSET_EL0, Overflow Flag Status Set and Clear Registers, PMOVSSET_EL0 and PMOVSCLR_EL0 on page 114
c14 {c8-c10} {0-7}e
0 3 RW Event Counter Register, PMEVCNTRn_EL0 on page 109 c11 {0-6}e
{c12-c14} {0-7}e
0 3 RW PMEVTYPERn_EL0 Event Type and Cycle Counter Filter Registers, PMEVTYPERn_EL0 and PMCCFILTR_EL0 on page 110 c15 {0-6}e
7 0 3 RW PMCCFILTR_EL0
c9 0 RW Performance Monitors Cycle Counter, PMCCNTR_EL0 on page 108;
MRRC and MCRR (AArch32) only.
a. The “64” column shows the op1 value in AArch64 state, the “32” column the op1 value in AArch32 state.
b. PMOVSCLR_EL0 is the AArch64 name, PMOVSR is the AArch32 name. They are the same register.
c. PMUSERENR_EL0 is always RO at EL0, RW at EL1 and above.
d. In [v7A] PMOVSSET is implemented only if the PMUv2 implementation includes the Virtualization Extensions. It is required in all implementations of PMUv3.
e. CRm and op2 encode n, the counter number. For values of n corresponding to not implemented counters see PMEVCNTRn_EL0 and PMEVTYPERn_EL0 (direct access) on page 118.
Table 33: Performance Monitors system register map, op0=3, AArch64; and CP15 register map, AArch32
6.7.2 Accessing Performance Monitors registers
Each EL has the ability to control Performance Monitors system register accesses at lower Exception levels:
At EL0:
— writes to PMUSERENR_EL0 are UNDEFINED
— read/write of PMINTENSET_EL1 and PMINTENCLR_EL1 are UNDEFINED
— if PMUSERENR_EL0.EN == 0:
if PMUSERENR_EL0.SW == 0 then writes to PMSWINC_EL0 are trapped to EL1
if PMUSERENR_EL0.CR == 0 then reads of PMCCNTR_EL0 are trapped to EL1
if PMUSERENR_EL0.ER == 0 then reads of PMEVCNTRn_EL0 and
PMXEVCNTR_EL0, and reads and writes of PMSELR_EL0, are trapped to EL1
otherwise, all other Performance Monitors register accesses, other than reads of PMUSERENR_EL0, are trapped to EL1.
Note: If HCR_EL2.TGE == 1, then all exceptions that would be taken to EL1 are instead taken to EL2. See [v8Exception].
Otherwise, at EL1 and EL0 in Non-secure state, if EL2 is implemented:
— if MDCR_EL2.TPMCR == 1 then accesses to PMCR_EL0 are trapped to EL2
— if MDCR_EL2.TPM == 1 then accesses to all Performance Monitors registers, including PMCR_EL0, are trapped to EL2.
Otherwise, at EL2, EL1 and EL0, if EL3 is implemented and using AArch64:
— if MDCR_EL3.TPM == 1 then accesses to all Performance Monitors registers are trapped to EL3.
These traps are not possible if EL3 is using AArch32.
Otherwise, the access is permitted.
Note: These traps and enables only apply to system register accesses using system register access instructions. For accesses by the external debug interface, see External access to the Performance Monitors on page 125.
For details of the headings used in Table 34, see Accessing debug system registers on page 63. In addition:
Instruction
Shows the access instruction, read (MRS), write (MSR), or both (“-“). (Or the equivalent MRC and MCR instructions in AArch32 state.)
Traps from below to EL1, if 0
As the “Traps from below to ELy” column for Table 22, except that the trap on accesses to the register is enabled if the expression is zero. The control bits are in PMUSERENR_EL0.
That is, if the “Default at EL0” column shows the access as “-“ then the access is trapped from EL0 to EL1 unless (any of) the access enable(s) in PMUSERENR_EL0 are set to 1.
Registera Instruction Default at EL0
Traps from below to
Default EL1, if 0 EL2, if 1 EL3b, if 1
PMCR_EL0 - - EN TPMCR || TPM TPM RW
PMCNTENSET_EL0 - - EN TPM TPM RW
PMCNTENCLR_EL0 - - EN TPM TPM RW
PMOVSCLR_EL0 - - EN TPM TPM RW
PMSWINC_EL0 - - EN || SW TPM TPM WO
PMSELR_EL0 - - EN || ER TPM TPM RW
Registera Instruction Default at EL0
Traps from below to
Default EL1, if 0 EL2, if 1 EL3b, if 1
PMCEID0_EL0 - - EN TPM TPM RO
PMCEID1_EL0 - - EN TPM TPM RO
PMCCNTR_EL0 MRS - EN || CR
TPM TPM RW
MSR - EN
PMXEVTYPER_EL0 - - EN TPM TPM RW
PMXEVCNTR_EL0 MRS - EN || ER
TPM TPM RW
MSR - EN
PMUSERENR_EL0 MRS RO -
TPM TPM RW
MSR UND -
PMINTENSET_EL1 - UND - TPM TPM RW
PMINTENCLR_EL1 - UND - TPM TPM RW
PMOVSSET_EL0 - - EN TPM TPM RW
PMEVCNTRn_EL0 MRS - EN || ER
TPM TPM RW
MSR - EN
PMEVTYPERn_EL0 - - EN TPM TPM RW
PMCCFILTR_EL0 - - EN TPM TPM RW
a. AArch64 names shown, other than in cases where access permissions differ in the two states.
b. Only if EL3 is using AArch64.
Table 34: Performance Monitors system registers access permissions summary
6.7.3 Performance Monitors system register resets
Table 35 summarizes the Performance Monitors register resets for writable register fields:
the “64” column showing architectural reset values when resetting into AArch64 state
the “32” column when resetting into AArch32 state
entries labeled “-” have an IMPLEMENTATION DEFINED reset value on the specified reset, which may be UNKNOWN.
These tables do not include:
Read-only identification registers and fields that have a fixed value.
— The reset value is that fixed value.
— For example, PMCR_EL0.N.
Write-only registers and fields which only have an effect on writes.
— These have no meaningful reset value.
— For example, PMSWINC_EL0.
IMPLEMENTATION DEFINED registers.
— The reset domains are IMPLEMENTATION DEFINED.
— The reset values are IMPLEMENTATION DEFINED (and may be UNKNOWN).
All other fields in registers are reset to an IMPLEMENTATION DEFINED value which can be UNKNOWN, and the register is in the specified reset domain.
Register Domain Field 64 32 Description
PMCR_EL0 Warm DP - 0 Disable PMCCNTR_EL0 when prohibited
X - 0 Export enable
D - 0 Clock divider
E 0 0 Performance Monitors enable
PMCNTEN*_EL0 Warm - - - All fields in register
PMOVS*_EL0 Warm - - - All fields in register
PMSELR_EL0 Warm SEL - - Selected event counter
PMCCNTR_EL0 Warm - - - All of register
Register Domain Field 64 32 Description PMEVTYPERn_EL0 Warm - - - All fields in register
PMCCFILTR_EL0 Warm [31:26] - 0x00 PMCCNTR_EL0 filtering controls
PMEVCNTRn_EL0 Warm - - - All of register
PMUSERENR_EL0 Warm ER - 0 Enable counter read access in EL0
CR - 0 Enable PMCCNTR_EL0 read access in EL0 SW - 0 Enable PMSWINC_EL0 write access in EL0 EN - 0 Enable Performance Monitors access in EL0
PMINTEN*_EL1 Warm - - - All fields in register
Table 35: Summary of Performance Monitors system register resets
6.7.4 Relationship between AArch32 and AArch64 Performance Monitors registers
Table 36 shows the mapping between AArch32 and AArch64 register names.
AArch32 AArch64 AArch32 AArch64
PMCR PMCR_EL0 PMXEVCNTR PMXEVCNTR_EL0
PMCNTENSET PMCNTENSET_EL0 PMUSERENR PMUSERENR_EL0
PMCNTENCLR PMCNTENCLR_EL0 PMINTENSET PMINTENSET_EL1
PMOVSR PMOVSCLR_EL0 PMINTENCLR PMINTENCLR_EL1
PMSWINC PMSWINC_EL0 PMOVSSET PMOVSSET_EL0
PMSELR PMSELR_EL0 PMEVCNTRn PMEVCNTRn_EL0
PMCEID0 PMCEID0_EL0 PMEVTYPERn PMEVTYPERn_EL0
PMCEID1 PMCEID1_EL0 PMCCFILTR PMCCFILTR_EL0
PMCCNTR (MRC/MCR) PMCCNTR_EL0[31:0] PMCCNTR (MRRC/MCRR) PMCCNTR_EL0[63:0]
PMXEVTYPER PMXEVTYPER_EL0
Table 36: Equivalence between Performance Monitors AArch32 CP15 and AArch64 system registers