5. Accepted Technical Design
5.1.3 Level Shifter Overview
The level shifter subsystem consists of a logic level generator, output driver, single-ended receiver, differential receiver, and various configurable resistors. A level 2 block diagram of the level shifter subsystem is shown in Figure 9. For each I/O pin, there exists one output driver, one single-ended receiver, and various configurable resistors. As some protocols use a single I/O line for bidirectional communication, the output of the output driver is tied to the input of the
single-ended receiver. When bidirectional communication is required, the output driver can be put into a floating state in order to make receiving possible. For each adjacent pair of I/O pins, there is a differential receiver and a multiplexer to switch between single-ended input or
differential input to the microcontroller. In differential mode, only the multiplexed input from the differential receiver is read by the microcontroller, while the other input from the second
single-ended receiver is ignored. Each I/O pin has two logic levels, a low-level voltage V L and a
Figure 9: Level Shifter Subsystem Level 2 Block Diagram
Tables 12, 13, 14, 15, 16, and 17 list functional requirements for the blocks shown in Figure 9.
Table 12: Logic Level Generator Functional Requirements
Module Logic Level Generator
Designer Ian Glen
Inputs - 3.3V power input
- ±15V power input
- Control signal from microcontroller subsystem (I 2 C bus)
Outputs - V H voltage rail for each I/O pin (configurable between -15V and +15V)
- V L voltage rail for each I/O pin (configurable between -15V and +15V)
Description The logic level generator is responsible for generating the logic level voltages for each individual I/O pin, as defined by the microcontroller.
Table 13: Output Driver Functional Requirements
Module Output Driver
Designer Ian Glen
Inputs - 3.3V power input
- ±15V power input
- Low-voltage signals from microcontroller
Outputs - High-voltage signal to target device
Description The output driver is responsible for shifting a low-voltage digital signal from the microcontroller to the high-voltage logic levels required by the target device, as well as acting as a power amplifier to provide the required drive current.
Table 14: Single-Ended Receiver Functional Requirements
Module Single-Ended Receiver
Designer Ian Glen
Inputs - 3.3V power input
- ±15V power input
- High-voltage signal from target device
Outputs - Low-voltage signal to microcontroller
Description The single-ended receiver is responsible for shifting a high-voltage signal from the target device to a low-voltage signal so that it can be received by the microcontroller.
Table 15: Differential Receiver Functional Requirements
Module Differential Receiver
Designer Ian Glen
Inputs - 3.3V power input
- ±15V power input
- High-voltage signal from target device (first I/O pin - non-inverted signal) - High-voltage signal from target device (second I/O pin - inverted signal)
Outputs - Low-voltage single-ended signal to microcontroller
Description The differential receiver is responsible for shifting a high-voltage differential signal from the target device to a low-voltage single-ended signal so that it can be received by the
microcontroller.
Table 16: Differential Multiplexer Functional Requirements
Module Differential Multiplexer
Designer Ian Glen
Inputs - 3.3V power input
- Control signal from microcontroller
Outputs - Low-voltage signal from single-ended receiver - Low-voltage signal from differential receiver
Description The multiplexer is responsible for selecting between the single-ended receiver input or differential receiver input depending on the operating mode of the I/O pin.
Table 17: Configurable Resistors Functional Requirements
Module Configurable Resistors
Designer Ian Glen
Inputs - 3.3V power input
- ±15V power input
- Control signals from microcontroller
Outputs n/a
Description The configurable resistors are responsible for properly biasing the I/O pins depending on the electrical requirements of the particular protocol in use.
The logic level generator uses a combination of a multi-channel DAC and buffer amplifier to generate low current voltage rails for use as logic levels in high-voltage signalling. A level 3
block diagram is shown in Figure 10. The DAC is a Microchip MCP4728, which provides four 12-bit channels. Each I/O pin uses two DAC channels to generate the V L and V H logic level
voltages. Via I 2 C, the microcontroller sets the DAC channel output voltages, which can be
anywhere between 0V and 3.3V. Typically DACs must be buffered in order to prevent a load from affecting the output voltage. A combination of buffer and scaler is used to scale the output voltage to -15V to +15V, allowing for a full range of logic levels to be selected. Given that each I/O pin is limited to 50mA and each DAC channel is only tied to one I/O pin, a simple
buffer/scaler circuit is capable of providing enough current. (IG)
Figure 10: Logic Level Generator Level 3 Block Diagram
The DAC register value can be calculated for a given output voltage with the following equation:
Tables 18 and 19 list the functional requirements for the blocks shown in Figure 10.
Table 18: Digital to Analog Converter (DAC) Functional Requirements
Module Digital to Analog Converter (DAC)
Designer Ian Glen
Inputs - 3.3V power input
- Control signal from microcontroller (I 2 C bus)
Outputs - V H prescaled voltage (0V to 3.3V)
- V L prescaled voltage (0V to 3.3V)
Description The DAC is responsible for providing configurable voltages that will be scaled to generate the logic level voltages.
Table 19: DAC Buffer/Scaler Functional Requirements
Module DAC Buffer/Scaler
Designer Ian Glen
Inputs - 3.3V power input
- ±V power input
- Prescale voltages from DAC
Outputs - V H voltage rail for each I/O pin (configurable between -15V and +15V)
- V L voltage rail for each I/O pin (configurable between -15V and +15V)
Description The DAC buffer/scaler is responsible for buffering the DAC output voltages and scaling them to create the logic level voltages.
Figure 11: Output Driver Level 3 Block Diagram
Table 20 lists the functional requirements for the FET block shown in Figure 11.
Table 20: FET Functional Requirements
Module FET
Designer Ian Glen
Inputs - V H and V L logic level power input
- Low-voltage signal from microcontroller (3.3V, up to 10MHz)
Outputs - High-voltage signal to target device (up to ±15V, up to 10MHz, up to 50mA)
Description The FET is responsible for shifting the low-voltage microcontroller signal to a higher voltage and acting as a power amplifier to provide the required drive current.
Figure 12: Single-Ended Receiver Level 3 Block Diagram
Tables 21 and 22 list functional requirements for the blocks shown in Figure 12.
Table 21: Receiver Comparator Functional Requirements
Module Receiver Comparator
Designer Ian Glen
Inputs - 3.3V power input
- High-voltage signal from target device
- Threshold voltage generated from logic level voltage rails
Outputs - Low-voltage signal to microcontroller
Description The Comparator is responsible for shifting a high-voltage signal from the target device to a low-voltage signal so that it can be received by the microcontroller.
Table 22: Receiver Threshold Functional Requirements
Module Receiver Threshold
Designer Ian Glen
Inputs - V L and V H logic level voltage rails
Outputs - Receiver threshold voltage
Description The Receiver Threshold block is responsible for generating a threshold that is the average of the logic level voltage rails used for detection of the signal from the target device.
Figure 13: Differential Receiver Level 3 Block Diagram
Tables 23, 24, and 25 list the functional requirements for the blocks shown in Figure 13.
Table 23: Differential Receiver Amplifier Functional Requirements
Module Differential Receiver Amplifier
Designer Ian Glen
Inputs - ±15V power input
- High-voltage signal from target device (non-inverted signal) - High-voltage signal from target device (inverted signal)
Outputs - Single-ended high-voltage signal to receiver comparator
Description The Differential Receiver Amplifier is responsible for measuring the differential voltage between two I/O pins in order to convert it to a single-ended signal.
Table 24: Differential Receiver Comparator Functional Requirements
Module Differential Receiver Comparator
Designer Ian Glen
Inputs - 3.3V power input
- High-voltage single-ended signal from differential amplifier - Threshold voltage generated from logic level voltage rails
Outputs - Low-voltage signal to microcontroller
Description The Differential Receiver Comparator is responsible for shifting the high-voltage single-ended signal from the differential amplifier to a low-voltage signal so that it can be received by the microcontroller.
Table 25: Differential Receiver Threshold Functional Requirements
Module Differential Receiver Threshold
Designer Ian Glen
Inputs - V L and V H logic level voltage rails from the non-inverted I/O pin
- V L and V H logic level voltage rails from the inverted I/O pin
Outputs - Receiver threshold voltage
Description The Differential Receiver Threshold block is responsible for generating a receiver threshold voltage that is the average of the difference between the logic level voltages for the two I/O pins used for differential communication.
Figure 14: Configurable Resistors Level 3 Block Diagram
Tables 26, 27, and 28 list the functional requirements for the blocks shown in Figure 14.
Table 26: Pull-up Resistor Functional Requirements
Module Pull-up Resistor
Designer Ian Glen
Inputs - High-voltage signals from target device
Outputs n/a
Description The Pull-up Resistor block is a resistor that can be enabled by the microcontroller to provide a pull-up resistance if required by the protocol.
Table 27: Pull-down Resistor Functional Requirements
Module Pull-down Resistor
Designer Ian Glen
Inputs - High-voltage signals from target device
Outputs n/a
Description The Pull-down Resistor block is a resistor that can be enabled by the microcontroller to provide a pull-down resistance if required by the protocol.
Table 28: Termination Resistor Functional Requirements
Module Termination Resistor
Designer Ian Glen
Inputs - High-voltage signal from target device (non-inverting signal) - High-voltage signal from target device (inverting signal)
Outputs n/a
Description The Termination Resistor block is a resistor that can be enabled by the microcontroller to provide the correct termination resistance between differential signal lines if required by the protocol.