USB Protocol

The I/O Master utilizes USB for communication with the user’s computer. The USB protocol is   very broad and has many different standards, so more information is necessary to determine how   USB can be used for communication. The STM32H7 microcontroller features built-in hardware   support for USB 1.1 Full Speed that has a theoretical maximum throughput of 12 Mbps. With the   addition of some external hardware, the microcontroller can also operate at USB 2.0 High Speed   with a theoretical maximum of 480 Mbps.  

Since the USB 1.1 throughput is 12 Mbps, it potentially could be used, though the theoretical   maximum is close to the necessary speed of 10 Mbps. To determine if using USB 1.1 is possible,   the configurations and corresponding overheads needs to be considered. The best suited USB 1.1  

device class for the I/O Master is the Communications Design Class (CDC), which is for sending   and receiving generic data.  

The STM32 CDC library supports a max data packet size of 64 bytes. In addition, the packet can   be sent with a top speed of 1 packet / ms, or 1000 packets / second. This equals out to a  

maximum data throughput of 500 Kbit, which is 20 times slower than the 10 Mbit data   throughput required.  

USB 2.0 High Speed allows for up to 480 Mbit transfer speeds and offers more device classes to   configure. Many high speed and low latency applications utilize the USB 2.0 CDC Network   Control Model (NCM) specification. Real world maximums in bandwidth for USB CDC NCM is   around 200 Mbit, which is more than enough to be used for 10 Mbit data transfer. USB CDC   NCM is very fast because it implements the IEEE 802.3 network frame definitions which now   support gigabit speeds over ethernet.  

By using USB CDC NCM, all operating systems will already have native high speed support for   communication since it is the same network stack that is used by ethernet. The I/O Master is seen   as a custom network device, and is easy to interface with it through common libraries in  

computer software. The real bottleneck of such an implementation is the speed of the USB   signal, which can be up to 480 MHz, much higher than the 10 MHz speed. If the overhead of   each packet is grossly overestimated as high as 50%, speed of over 100 Mbit is still achievable,   thus making USB transfer feasible for the I/O Master as a communications method to the   computer. (CS)  

2.4.3 DMA  

One common method to output high speed data on GPIO pins is using bit banging. The concept   of bit banging is counting CPU clocks to time reading and writing of data out to GPIO. However,   bit banging requires a significant amount of CPU resources and is difficult to time correctly.   Utilizing bit banging requires a complex scheduling algorithm to ensure that timing for inputting   and outputting data is exact. With the desire to design the I/O Master to support a varying  

frequency up to 10 MHz, it is very difficult to achieve a general purpose implementation with bit   banging.  

Rather than bit banging, DMA can be used to stream data to GPIO pins. With peripheral DMA,   the DMA can be clocked and configured to send a block of data every time a timer period   finishes.   

In Figure 6, an example flowchart of streaming data using DMA is shown. The CPU is   responsible for setting up the DMA buffer and enabling DMA, shown in the blue region. The   DMA has its own clock controlled from a timer to send data at every pulse which is shown in the   purple region. While data is being streamed, more data can be prepared by the CPU to be  

streamed since the CPU is not locked up. If bit banging is used, the CPU is responsible for   preparing the data and outputting it, making it difficult to output data at a configured frequency   accurately and avoid lock ups.  

There is also potential to use DMA to move data in and out of USB buffers. Since DMA does not   utilize CPU resources, it is most ideal to use DMA in as many situations as possible. Using   DMA for a USB buffer does not require a link to a timer clock as the goal for USB is to move   data in and out as fast as possible. Hardware USB already has its own clocks to input and output   the data at the protocol specification frequency. (CS)  

2.4.4 Scheduler  

In order to ensure that transfer speeds can handle the 10 MHz requirements of the I/O Master, a   scheduler is necessary to keep watch on how full the input and output buffers are, handle   notifications of new data, and ensure that data is outputted in a reasonable time.  

The microcontroller only has a single core processor, but data could be coming in or moving out   of multiple sources at the same time. As a result, a scheduler is necessary in order to effectively   accomplish the goal of moving data at 10 MHz speed, which is necessary to support RS-485. The  

CPU is responsible for enforcing the schedule. Other onboard devices that do not utilize CPU   resources (DMA, Timers, Hardware USB) handle the actual transmission of the data.  

As data from the target device moves into the input data buffer on the microcontroller, the   scheduler ensures that the data is formed into packets and sent over USB to the computer before   the buffer fills up. At USB High Speed specification, data can theoretically be sent at up to 480   MHz. However, there is some overhead to sending a packet, so it would not be ideal to send   every frame of data as an individual packet. In addition, sending the USB packet to a computer is   a lower priority than reading in the input data. As a result, the input buffer should be configured   to be larger than the amount of data that can fit in one USB packet, and the packet should only be   output once that buffer is halfway full or if reading data is halted by the user.  

Since the microcontroller will be significantly faster than the incoming data rate, the packet can   be sent before the buffer is full again. This method ensures that locks on data processing are not   needed, which makes it easy to avoid potential data loss through overflow.  

In the other direction, data comes from the computer over USB and is then sent to the target   device. Since the USB protocol and computer are significantly faster than the max output   frequency of 10 MHz, there is a danger of running out of memory through overflow of USB   packets. To prevent this, the computer must limit the rate of data sent to the microcontroller.   To prevent an overflow of data coming from the computer, the microcontroller can respond with   an OK packet if the data is accepted into the buffer. If the buffer is full, then the microcontroller   can hold the packet until it can be processed. The computer does not send any additional packets  

until the OK packet is received. If the microcontroller receives additional data packets, they can   be ignored. (CS)