5. Accepted Technical Design
5.2 Hardware Implementation
5.2.1 Power Inputs
The I/O Master v1.0 can be powered through either the USB port (5V, 500mA) or, optionally, through the DC jack (12V, 500mA) when more power is required. A power switch circuit is used to switch between DC jack power and USB power when they are connected. The power input circuit is shown in Figure 21.
Figure 21: Power Input Circuit
A P-channel FET (Q27) is used to turn off the USB power input when the DC jack is connected, preventing high currents from potentially being drawn from the USB port. Power supply ORing diodes (D1 and D2) are used to prevent either supply from backfeeding if their input voltage differs. A 0.5A PTC resettable fuse (F1) protects the power inputs in the event of a circuit failure on the I/O Master. This type of the fuse allows the I/O Master to continue working after the fault has been cleared, as it resets on its own, and isn’t physically damaged when tripped, unlike traditional fuses. (IG)
5.2.2 3.3V Regulator
The 3.3V rail on the board is generated using an AZ1117 linear voltage regulator with a fixed output of 3.3V, shown in Figure 22. Since the 3.3V rail only powers the microcontroller, USB PHY, and configuration logic for the level shifter subsystems, the power requirements for the rail are low. Therefore, a linear regulator was selected to reduce complexity and part count. The specific part chosen is rated for an input voltage range of 4.6-15V with a maximum output current of 800mA.
Figure 22: 3.3V Regulator Circuit
Since the power requirements are low, no power calculations were done at the time of schematic design. The PCB layout included large copper areas and thermal vias around the linear regulator to keep the chip cool in the event that there was actually any significant power dissipation. These measures can be seen in Figure 23.
Once the I/O Master v1.0 hardware could be tested on the bench, the actual power draw of the 3.3V rail could be determined. Some analysis was done to determine the amount of heat dissipated by the linear regulator. Table 32 lists the power draws of the 3.3V rail and calculated power dissipation of the linear regulator under the worst-case scenario (highest input voltage, i.e. when using the 12V DC jack input). Power dissipation of the linear regulator is calculated using the difference in voltage across the regulator ( V OUT - V IN ) and the current output of the regulator.
Table 32: 3.3V Rail Power Consumption Microcontroller 0.429 W
RGB LED 0.009 W
USB PHY 0.132 W
Level Shifter DACs 0.009 W
Level Shifter Analog 0.006 W
Level Shifter Biasing 0.001 W
3.3V Rail LED 0.004 W
Total 3.3V Rail Power Draw 0.590 W
3.3V Regulator Power Dissipation 0.304 W
From the power consumption values, the total current draw on the 3.3V rail is 179mA, which is well within the maximum output current of the regulator. The temperature of the die in the regulator can also be determined using the power dissipation value. The datasheet suggests a thermal resistance of 100°C/W when using a copper area similar to Figure 23. With an ambient temperature of 40°C and a power dissipation of 0.304W, this results in a die temperature of 70.4°C. This is well within the maximum die temperature of 150°C listed in the datasheet. Using
these results, this linear regulator design is within spec and seems to work well for this application. (IG)
5.2.3 ±15V Regulator
Since the power requirements of the +15V and -15V rails are significantly higher than the 3.3V rail, a switching regulator must be used to supply the rails. A switching regulator has
significantly greater efficiency and therefore less power dissipation than a linear regulator, at the cost of greater complexity and the introduction of switching noise into the system.
The design used on the ±24V regulator demo board, which utilized the ADP5070, was adapted for ±15V output. The ADP5070 uses a boost topology to generate the positive rail and an inverting topology to generate the negative rail. The existing regulator design was modified to use smaller components, as the current requirements on each rail were determined to be less than what was designed for on the demo board.
Figure 24: ADP5070 Datasheet Regulator Schematic / Internal Block Diagram
For each rail, the regulator was designed for an average inductor ripple current of approximately 30% of the total output current. This is a common rule-of-thumb in switching regulator design, as it is a good balance of minimizing component size, efficiency, and output voltage ripple. The switching frequency of 1.2MHz was selected in order to minimize component size at the cost of some additional power dissipation. The diodes D1 and D2 were selected for low forward voltage drop, low junction capacitance, and a high power dissipation rating in order to account for the output current rating. The inductors L1 and L2 were selected to minimize size, shielded construction to minimize stray field, and high enough current ratings in order to not saturate at the required output current. In addition, the datasheet recommended adding loop compensation components in order to cancel out non-idealities in the regulator IC and feedback loop. These
non-idealities result in right-half-plane zeros in the system which contribute to instability. Design values for each voltage rail at each input voltage condition are listed in Tables 33 and 34.
Table 33: +15V Output Switching Regulator Design Values
V IN = 5V V IN = 12V
Design Parameters
Output Voltage V OUT 15 V
Comparator Reference V REF 0.8 V
Output Current I OUT 0.400 A
Switching Frequency f SW 1.2 MHz
D1 Part No. NSR0530HT1G
D1 Forward Voltage V F 0.62 V
D1 Junction Capacitance C J 10 pF
L1 Part No. LQH3NPN100MMEL
L1 Inductance L 10 µH
Calculated Inductor Values
Duty Cycle D 67.99 23.18 % Input Current I IN 1.250 0.521 A On Time t ON 0.567 0.193 µs Ripple Current I L1 0.283 0.232 A Ripple Current (%) I L1 22.67 44.51 % Peak Current I L1 1.391 0.637 A
L1 Minimum Inductance L 1-MIN 2.567 0.257 µH
Calculated Loop Compensation Values
Zero Frequency f Z-RHP 61.155 207.000 kHz Compensation Resistance R C 115.25 162.55 KΩ Compensation Capacitance C C 903 189 pF
Table 34: -15V Output Switching Regulator Design Values
V IN = 5V V IN = 12V
Design Parameters
Output Voltage V OUT -15 V
Comparator Reference V REF 0.8 V
Output Current I OUT 0.400 A
Switching Frequency f SW 1.2 MHz
D2 Part No. NSR0530HT1G
D2 Forward Voltage V F 0.62 V
D2 Junction Capacitance C J 10 pF
L2 Part No. ASPI-4030S-150M-T
L2 Inductance L 15 µH
Calculated Inductor Values
Duty Cycle D 75.75 56.55 % Input Current I IN 1.650 0.921 A On Time t ON 0.631 0.471 µs Ripple Current I L2 0.210 0.377 A Ripple Current (%) I L2 12.76 40.95 % Peak Current I L2 1.755 1.109 A
L2 Minimum Inductance L 2-MIN 3.917 3.497 µH
Calculated Loop Compensation Values
Zero Frequency f Z-RHP 8.000 8.000 kHz
Compensation Resistance R C 3.52 1.76 KΩ
Compensation Capacitance C C 0.226 0.452 µF
Figure 25: Final ±15V Regulator Schematic
The PCB layout of the switching regulator had to be carefully considered in order to ensure that the regulator would operate properly. The feedback loop formed between the regulator IC,
inductor, diode, and feedback resistors must be as small as possible in order to reduce the amount of parasitic inductance that is introduced into the loop. Parasitic inductance translates into delay in the feedback loop, which can reduce the performance of the regulator and cause instability. Figure 26 shows the recommended layout from the datasheet, and Figure 27 shows the actual layout of the ±15V regulator circuit. (IG)
Figure 26: AD5070 Datasheet Recommended Layout
Figure 27: ±15V Regulator PCB Layout