EE-612: Nanoscale Transistors (Advanced VLSI Devices) Spring 2005

1

EE-612:

Nanoscale Transistors ( Advanced VLSI Devices)

Spring 2005

Mark Lundstrom

Electrical and Computer Engineering Purdue University, West Lafayette, IN USA

765-494-3515

[email protected]

evolution of silicon technology

Bell Labs, 1947 Intel, 2002

3

Evolution of silicon technology

Year

Minimum Feature Size

1950 1970 1990 2010 2030 2050 1 nm

10 nm 100 nm 1 µm 10 µm

100 µm 1

1K

1M

1P 1G

1T

?

2004: 37 nm 2006: 28 nm 2008: 22 nm 2010: 18 nm 2014: 11 nm 2016: 9 nm 2018: 7 nm

2004 ITRS:

www.public.itrs.net

course objectives

» To understand nanoscale MOSFET device physics

» To appreciate how device performance affects circuits and systems

» To understand device scaling challenges

» To be introduced to new material/device approaches

5

course prerequisites

» Introductory level understanding of

semiconductor physics and devices as well as basic electronic circuits.

(EE255 and EE305/606 at Purdue)

(

basic MOS physics, devices, and CMOS

circuits will be briefly reviewed)

course outline

Part 1:

2 exams

Part 2:

final exam

Part 3:

online at www.nanohub.org live

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course text

Fundamentals of

Modern VLSI Devices

Yuan Taur and Tak Ning

Cambridge Univ. Press, 1998 www.cup.cam.ac.uk/

course grading

Exam 1: 25%

-classic, long-channel MOSFETs

Exam 2: 25%

-submicron MOSFETs, circuits and systems

Homework: 25%

Final: 25%

-nanoscale MOSFETs

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course overview

Part 1a:

-introduction

-semiconductor equations / device simulation -1D MOS electrostatics / capacitors

-polysilicon gates / non-equilibrium effects MOSFET IV: exact, square law, bulk charge

ballistic velocity saturation

subthreshold conduction

Vt, body effect, effective mobility

semiconductor equations

∇ • r

D = ρ

∇ • r

J

− q

( ) ^{= ( G − R )}

∇ • r

J

q

( ) ^{= ( G − R )}

conservation laws:

r

D = κε₀ r

E = −κε₀ r

∇ V

ρ = q p

(

)

J r _n = nqµ_n r

E + qD_n

∇ r n J r _p = pqµ_p r

E − qD_p

∇ r p

R = f (n, p) etc.

constitutive relations:

n, p,V

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device simulation

* SIMPLE MINIMOS SIMULATION

DEVICE CHANNEL=N GATE=NPOLY

+ TOX=150.E-8 W=1.E-4 L=0.85E-4 BIAS UD=4. UG=1.5

PROFILE NB=5.2E16 ELEM=AS DOSE=2.E15 + TOX=500.E-8 AKEV=160.

+ TEMP=1050. TIME=2700

IMPLANT ELEM=B DOSE=1.E12 AKEV=12 + TEMP=940 TIME=1000

OPTION MODEL=2-D OUTPUT ALL=YES END

MINIMOS 6.0

1D MOS electrostatics (L >> t _ox )

V = 0

V_G

x

V = 0

E_C

E_V E_F E_FG

qψ_S

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1D MOS electrostatics

E_C

E_V E_F E_FG

qψ_S

ψ_S < 0 accumulation

E_C

E_V E_F E_FG

ψ_S = 0 flat band

E_C

E_V E_F E_FG

qψ_S

ψ_S > 0 depletion/

inversion

Poisson-Boltzmann equation

E_C

E_V E_F E_FG

qψ_S

ψ_S > 0

∇ • r

D = ρ

∇ • r

J

− q

( ) ^{= ( G − R )}

∇ • r

J

q

( ) ^{= ( G − R )}

d²ψ

dx² = −q

ε N_A

(

)

A

e^{qψ /kBT}

( )



  

 

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1D MOS electrostatics

E_C

E_V E_F E_G

qψ_S

ψ_S > 0 log₁₀ Q_S

( )

C/cm²

ψ_S

~ ψ_S

~ e^{qψS / 2 kBT}

~ e^{−qψS / 2kBT}

depletion approximation

E_C

E_V E_F E_G

qψ_S

ψ_S > 0

ρ _x

−qN_A E

W

W

E_S

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depletion approximation

dE

dx = −qN_A ε

D^S = ε_SiE_S = −ρ_S = qN_AW

ρ _x

−qN_A

W

D_S

ψ_S = 1

2E_SW

W = 2ε_Siψ_S qN_A

Q_S

( )

W

E_S

δ -depletion approximation

E_C

E_V E_F E_G

qψ_S

ψ_S > 0 log₁₀ Q_S

( )

C/cm²

ψ

~ e^{qψS / 2 kBT}

~ e^{−qψS / 2kBT}

Q_S = 2qN_Aε_Siψ _S

ψ

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1D MOS electrostatics

C

V_G C_ox

acc inv

depl FB

Q_i

V_G

Q_i = −C_ox

(

)

V_T

above threshold:

Inversion layer charge

Q

= − C

( V

− V

) ^{≈ ?}

V_GS 1.2V V_T = 0.3V T_ox = 1.5 nm

Q

≈ 2 × 10

C/cm

Q

q ≈ 1 × 10

/cm

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MOSFET IV: low V _DS

Q_i

( )

(

)

V_G V_D 0

I_D = W Q_i

( )

( )

I^D = W C_ox

(

)

I_D = W

L µ_effC_ox

(

)

E_x = V_DS L

MOSFET IV: high V _DS

V_G V_D 0

I_D = W Q_i

( )

( )

I^D = W C_ox

(

)

V x

( )

(

)

E_x =

(

)

L I_D = W

L µ_effC_ox

(

)

2

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MOSFET IV

I_D = W

2L µ_effC_ox

(

)

I_D

V_DS

V_GS

I_D = W

L µ_effC_ox

(

)

“square law”

real MOSFETs

Intel Technical J., Vol. 6, May 16, 2002.

130 nm technology (L_G = 60 nm)

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velocity saturation

electric field V/cm --->

velocity cm/s --->

10⁷

10⁴

1.5V

60nm ≈25×10⁴ V/cm

υ = µE

υ = υ

MOSFET IV: high V _DS

V_G V_D 0

I_D = W Q_i

( )

( )

I_D = W C_ox

(

)

I_D = W υ_satC_ox

(

)

E >>10⁴

27

real MOSFETs

Intel Technical J., Vol. 6, May 16, 2002.

130 nm technology (L_G = 60 nm)

I_D ≈ W Q_i(0)υ_sat ≈1.6 mA/µm

MOSFET IV: subthreshold

|Q_i|

V_G

Q_i = −C_ox(V_GS −V_T)

V_T

log 10|Q i| ^{Qi = −Cox VGS −VT( )}

Q_i ~ e^{q V( GS−VT)/ kBT}

V_G

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MOSFET IV: subthreshold

V_G V_D 0

V_GS -->

S > 60 mV/decade

Log 10I DS-->

on-current

off-current

MOSFETs fundamentals

For a review, consult:

R. F. Pierret, Semiconductor Device Fundamentals, Addison-Wesley.

31

course overview

Part 1b:

-2d electrostatics

-channel length / effective channel length -parasitic S/D resistance / gate resistance -MOSFET scaling

Vt considerations / channel profile design Interconnects

CMOS circuits (digital)

CMOS systems and ultimate limits CMOS circuits (RF)

2D electrostatics

V_T = φ_ms + 2ψ_B − Q_S(2ψ_B) C_ox

channel length --->

V T-->

classic short channel effect

“V_T roll-off”

“reverse” short channel effect

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2D electrostatics

M. Ieong, et al., Science, Vol. 306, p. 2058, Dec. 17, 2004

“electrostatic integrity”

device scaling

~ L

L → L 2 A → A 2

Each technology generation:

Number of transistors per chip doubles

(scaling)

(Moore’s Law)

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device scaling

Goals of device scaling:

shrink size by factor, κ shrink area by κ²

reduce voltages by factor, κ reduce current by factor, κ

result is lower power-delay product, but…

V_GS -->

S > 60 mV/decade

Log 10I DS-->

Off-currents are increasing exponentially!

circuits

V_DD V_DD

V OUT -->

V_IN-->

V_DD

V_IN V_OUT

P

N

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circuit speed

V_IN

V_OUT

C_load

If C_load = C_G:

τ = C_GV_DD

I_D(on) ≈ L

υ ≈ 0.5 ps

--> f = 2000 GHz!

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interconnects

Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 Metal 7

transistor

39

speed

speed is controlled by the DC “on-current”

τ = C

V

I

(on)

power

P

= N

I

(off )V

P

= α f C

V

DD

2

1) standby power:

2) dynamic power:

P1

N1

I_D(off)

V_in

P1

N1

CL Icharge

Idischarge V_dd

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power

14

®

®

Power density will increase

4004 8008

8080

8085 8086

286 386

486

Pentium® proc P6

1 10 100 1000 10000

1970 1980 1990 2000 2010

Year

Power Density (W/cm2)

Hot Plate Nuclear Reactor Rocket Nozzle

Power density too high to keep junctions at low temp Power density too high to keep junctions at low temp

course overview

Part 2: nanoscale MOSFETs

-gate capacitance -gate leakage

-high-k gate dielectrics -reliability

-SOI technology -SOI devices

-strained channel MOSFETs -new channel materials

Ballistic MOSFETs

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nanoscale CMOS

gate capacitance

1.2 nm

45

gate capacitance

Q

= − C

( V

− V

)

C

= C

C

C

+ C

≈ C

?

C

= ε

t

C

= ε

t

Is t_ox >> t_inv still a good assumption at the nanoscale?

quantum effects

energy-->

0 W

x

E

x n(x)

W

n(x) = N_CF_{1/ 2}

[

]

classical

quantum

n(x) ~ sin² kx

47

quantum effects

E_C

E_V E_F E_G

ψ_S > 0

n(x)

gate leakage

49

SOI technology

M. Ieong, et al., Science, Vol. 306, p. 2058, Dec. 17, 2004

Device physics:

-floating body effects, ideal subthreshold swing Device structures:

-partially depleted, fully-depleted, UTB, DG, tri-gate, FinFET, …

strained channel MOSFETs

Silicon germanium Strained Silicon

51

ballistic MOSFETs

L = 10 nm

n(x, E)

course overview

Part 3:

- a collection of seminars on nanoscale CMOS and beyond

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ultimate CMOS

Jim Hutchby, 2003

Intel tri-gate

TSi=7nm Lgate=6nm

Source Drain

Gate

IBM (2002) L ~ 6 nm

Berkeley FinFET

carbon nanotube transistors?

Delft, 1998

Gate 8nm HfO₂

SiO₂

p⁺⁺ Si Pd _CNT Pd

50nm

Stanford, Purdue, Harvard, 2004

Drain Source

CNT

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molecular transistors?

DS G

EE-612

at the intersection of:

-devices and circuits

-microelectronics and nanoelectronics