EE 3714 Test #1 Solutions - Fall 1999 – Reese
1. (6 pts) What is the minum number of bits that I need if I want to encode 24 distinct items? 5 bits can encode 32 items, 4 bits can encode 16 items, so correct answer is 5 bits.
2. ( 6 pts) What range of signed integers can I represent using 6 bits and 2's complement representation? –32 to + 31.
3. ( 6 pts) The following 8-bit hex number $D3 represents a signed integer in 2’s complement format. What is its decimal value? The MSB is a ‘1’, so number will be negative. $D3 = 11010011. Take 2’s complement for magnitude, get 00101101 = $2D = 2*16 + 13 = 45. Answer is – 45.
4. ( 6pts ) The following 8-bit hex number $21 represents a signed integer in signed magnitude format. What is its decimal value? MSB is 0, so number is positive. To get magnitude, just covert to decimal. $21 = 2*16 + 1 = 33. Answer is +33.
5. ( 6 pts) Convert the following number decimal -15 (negative fifteen) to an 8-bit representation using one’s complement format. 15 converted to 8 bits is = $0F = % 00001111. Takes ones complement to get negative representation, so answer is % 11110000 = $F0.
6. (6 pts) Write a sum of two 8-bit hex numbers in 2’s complement format that will produce a signed overflow. $70 + $10 = $80. Positive + Positive = Negative.
7. ( 6 pts) Write a sum of two 8-bit hex numbers representing unsigned numbers that will produce a unsigned overflow. $FF + $01 = $00. 255 + 1 = 256. The value 256 is outside the range 0 to 255.
8.( 6 pts) Convert the following expression to a POS form: PQ + XY
Use distributive law PQ + XY = (PQ +X)(PQ + Y) = (P+X)(Q+X)(P+Y)(Q+Y)
9. ( 6 pts) Write the truth table for the following function: F (A,B,C) = (A xor B) and C A B C A xor B (A xor B) and C
0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 0 0
10. (6 pts) Simplify the following equation to as few as terms as possible. (A + (BC)’) ( A + BC)
Use the property that (A + X’)(A + X) = A. Let X = BC. Then answer is A .
11. (6 pts) Complete the timing diagram for the Y output.
12. (6 pts) Draw the CMOS transistor diagram for a 2 input NAND gate. Α
Β
Y
B A
1 ns 2 ns 3 ns 4 ns 5 ns 6 ns
Y
Gate propation delay = 2 ns
Xor
0 ns 7 ns 8 ns
A
PMOS
NMOS
B
B
Y
NMOS
13. (6 pts) Convert the following to a POS form (Hint: use DeMorgan’s Law): (X + Y'Z)' = (X’)( Y’Z)’ = X’ (Y + Z’)
14. (6 pts) In the circuit labeled FIGURE 1, what is the MAXIMUM path delay if the propagation delay of the inverters is 1 ns, the AND gate propagation delay is 2 ns, and the OR gate propagation delay is 5 ns?
See Figure 2.15 ( c ) in the textbook.
The maximum path delay is through the lower AND gate to the output: AND (2ns) + OR (5 ns) + OR (5 ns) + AND (2) = 14 ns
The paths through the upper AND gate is:
AND (2ns) + OR (5 ns) + NOT (1 ns) + AND (2ns) + AND (2 ns) = 12 ns
15. (10 pts) For the statements below, fill in the blank using words from the list below:
WAFER, DIE, PACKAGE, VIH, VIL, VOH, VOL, TTL, NMOS, PMOS, CMOS, NAND-NAND, NOR-NOR
a. ___PACKAGE____ Used to provide external connections of the inputs, outputs of the chip, placed on a printed circuit board.
b. _____CMOS________ The process technology in which NMOS, PMOS transistors are created; the dominant process techology for making designs with large numbers of logic gates.
c. ___VOH________ The minimum OUTPUT VOLTAGE that is considered to be a HIGH voltage.
d. ____NOR-NOR________ This two level form can implement POS equations assuming dual rail inputs.
e. _____WAFER_______ Processed in batches of 25 on the fabrication line; is circular and is usually either 6" or 8" in diameter, made of silcon.
16. (6 pts) Give me an example of a boolean equation that can be simplified using the consensus theorem. Give me the equation BEFORE and AFTER simplification via the consensus theorem.
EE 3714 Test #1 SOLUTIONS - Fall 2001 – Reese Student ID: _______________________ (no names please)
Work all problems. Closed book, closed notes; No calculators.You may use the supplied reference material.
1. (9 pts) Convert the decimal value below to its 8-bit representation in each of the following encoding schemes. Write your answers in either HEX (base 16) or binary.
Signed Magnitude 1's Complement 2's Complement -29
hex magnitude = 1D (16 + 13)
9D = 10011101 E2 = 11100010 E3=11100011
2. ( 5 pts) Repetitively apply De'Morgan's theorem to the equation until only single variables are complemented (the not operator is applied only to single variables).
( (A' + B'C) D ) ' = (A' + B'C)' + D' = A (B'C)' + D' = A(B+C') + D' = AB + AC' + D'
3. ( 5 pts) Simplify the following equation to a minimal expression: AB + ABC + B
B (A + AC + 1) B
4. ( 5 pts ) Use one or more gates below such that Y is a LOW voltage when either button A or button B is pressed. Be sure to give gate numbers such as 7400, 7432, 7402, 7408, 7404 etc.
A
Y
B
7404
7408
A
B
7404
7402
Y
Convert B to
low true
Convert A to
high true
Solution #1
Solution #2
A
Y
B
7404
7408
A
B
7404
7402
Y
Convert B to
low true
Convert A to
high true
5. ( 5 pts) Complete the timing diagram below for A' and Y assuming that all gate delays = 1 ns.
6. (5 pts) Write the following function in SOP form using the minterms indicated. Do NOT minimize. F(A,B,C) =
S
m(1, 4, 6) = A'B'C + AB'C' + ABC'7. (5 pts) Write the following function in POS form using the maxterms indicated. Do NOT minimize. F(A,B,C) =
P
M(1, 4, 6) = (A+B+C')(A'+B+C)(A'+B'+C)8. ( 5 pts) Write the MAXTERM POS form that represents the following truth table for F(A,B,C)
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
A
A’
Y
A
A’
Y
0 ns
0 11 ns 2 ns
3 ns
4 ns
5 ns 6 ns
7 ns
8 ns
9 ns
10 ns
1A
A’
Y
A
A’
Y
0 ns
0 11 ns 2 ns
3 ns
4 ns
5 ns 6 ns
7 ns
8 ns
9 ns
10 ns
1P
M(0, 4, 6)9. ( 5 pts) What is the voltage value (L or H) of output Y when A = L, B = H, C =H. To get credit for this problem, you MUST show which transistors are open or closed and the path from Y to either Vdd or Gnd.
10. ( 5 pts) Fill in the truth table for the following function: F (A,B,C) = (A+B)' C
F = (A+B)'C = A'B'C
A B C F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Vdd
A=L
B=H
B=H
Y = L
A=L
C= H
C=H
Vdd
Vdd
A=L
B=H
B=H
Y = L
A=L
C= H
C=H
11. ( 6 pts) Using the following gates: 7432, 7400, 7408, 7402, 7404 give three combinations that are 'complete' logic families. Your three combinations of complete families cannot overlap.
Family #1: ________7400 (NAND gates are complete)_____________ Family #2: _________7402 (NOR gates are complete)_______________ Family #3: _________7408,7404 OR 7432, 7404_______________
12. (8 pts) PROVE or DISPROVE the following Boolean theorem. You can either use truth tables or algebraic manipulation. You MUST show your work.
(A xor B) C = (AC) xor (BC)
(AB' + A'B) C = (AC) (BC)' + (AC)' (BC)
AB'C + A'BC = AC (B'+C') + (A'+C')BC = AB'C + ACC' + A'BC + BCC' = AB'C + 0 + A'BC + 0
= AB'C + A'BC
PROVED .
A B C (A xor B) C (AC) xor (BC)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 1
1 0 0 0 0
1 0 1 1 1
1 1 0 0 0
13. (12 pts) Use one of the following terms to fill in the blanks below (you can also use numbers such as '1', '2', '3', etc).
CMOS DIE WAFER PMOS NMOS TTL TPHL TPLH POWER FREQENCY ASCII XOR NAND NOR PACKAGES HIGH LOW ASCII
a. ___CMOS______ gates consist of PMOS and NMOS transistors.
b. The ___TPLH_________ delay is the time delay between a low to high voltage change on the output and a change on an input.
c. A CMOS 2-input NAND gate has ______4______ transistors.
d. A ____WAFER_______ is cut up into small squares call 'die', and each die is placed in a package - the package is normally what people refer to as a 'chip'.
e. It would take ______5______ binary digits to encode 17 distinct items.
f. The _____ASCII_____________ code is a common method for encoding alphanumeric data.
000, 001, ___011____, 010, __110______, 111, 101, ___100______
16. (10 pts) I would like to implement an 8-input AND gate (F = A B C D E F G H) but I only have gates with 4 or fewer inputs. The gate types you have available are NAND, NOR, AND, OR, NOT. Draw TWO different gate networks that implement this function. The gate types used in the two networks MUST BE DIFFERENT (i.e. if you use both NANDs and NORs in one network, they cannot be used in the other network).
And gates
NAND gates + NOR gate
And gates
EE 3714 Test #1 Solutions- Spring 2000 – Reese
1. (5 pts) What is the minum number of bits that I need if I want to encode 33 distinct items? 6 bits (26 = 64)
2. ( 5 pts) What range of signed integers can I represent using 4 bits and 2's complement representation? -8 to 7
3. ( 5 pts) The following 8-bit hex number $E7 represents a signed integer in 2's complement format. What is its decimal value? $E7 is a negative number, complement & Add one, get $19. Convert to decimal, get 25.
4. ( 5 pts ) The following 8-bit hex number $3A represents a signed integer in signed magnitude format. What is its decimal value? This is a positive number, convert to decimal: 58.
5. ( 5 pts) Convert the following number decimal -21 (negative twenty-one) to an 8-bit representation using one's complement format. Convert magnitude to hex: $15. Complement, get: $EA.
6. (5 pts) How do you detect overflow when adding 2's complement number? Add two negative numbers, get positive. Add two positive numbers, get negative.
7.( 5 pts) How do you detect overflow when adding unsigned numbers? Carry out of most significant bit position.
8. ( 5 pts) Convert the following expression to a POS form:
AC+D(B+E) = (AC +D)(AC+B+E) = (A+C)(A+D)(A+B+E)(C+B+E)
9. ( 5 pts) Write the truth table for the following function: F (A,B,C) = (AB)' + C
A B C (AB)' (AB)' + C 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 0 1
10. (5 pts) Simplify the following equation to as few terms as possible AB' + AB'CD + ABC'D'
Hint: the relation X + X'Y = X + Y is useful. Also final answer has two product terms, one term with 2 variables, the other term with 3 variables.
AB' (1 + CD) + ABC'D' AB' + ABC'D'
11. (10 pts) Complete the timing diagram for the A’, Y signals. Each gate has a delay of 1 ns. Complete the diagram out to 10 ns.
12. (5 pts) Draw the CMOS transistor diagram for a 2 input NOR gate. SEE NOTES.
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
XOR
A
A’
XOR
Y
A
A’
Y
0 ns
0 1
1 ns 2 ns
3 ns
4 ns
5 ns 6 ns
7 ns
8 ns
9 ns
10 ns
13. (5 pts) Used DeMorgan’s Law on the following equation until the NOT operator is only applied to single variables:
(X’Y + A’(B+C)) ’ = (X’Y)’ (A’(B+C))’ = (X+Y’)((A’)’ + (B+C)’) = (X+Y’) (A + B’C’)
14. (5 pts) In the circuit shown below, what is the MAXIMUM path delay if the propagation delay of the inverters is 1 ns, the AND gate propagation delay is 2 ns, and the OR gate propagation delay is 5 ns? 19 ns, SEE FIGURE 2.14(b) pg 38 in textbook.
15. (5 pts) Which two level gate forms are used to directly implement boolean equations in POS equations? (hint: You need to list ’2’ two level gates forms) OR-AND, NOR-NOR
16. (5 pts) Which two level gate forms are used to directly implement boolean equations in SOP equations? (hint: You need to list ’2’ two level gates forms) AND-OR, NAND-NAND 17. (5 pts) Explain the terms ’wafer’ and ’die’ in terms of integrated circuit manufacturing.
Wafer is a thin, round (6-8") piece of silicon that is processed thru the fabrication line. Each Wafer is divided into rectangular areas called ’die’ -each die contains the same integrated circuit.
18. ( 5 pts) Explain the terms ’fanout’ and ’fanin’.
Fanin - number of gate inputs, Fanout - number of inputs that a particular output is connected to.
19. ( 5 pts) Convert the following expression to a SOP form that has only two product terms. (A + BCD’)(A’ + D)
EE 3714 Test #2 - Fall 1999 – Reese
SSN: _______________________ (no names please) Work all problems.
1. (8 pts) Plot the following function on a K-Map.
F(A,B,C,D) = AD + B’C
2. ( 8 pts) Plot the following function on a K-Map. F(A,B,C,D) = Π M(0,3,4,8,12,13,15)
00 01 11 10
00
01
11
10
AB
CD
00 01 11 10
00
01
11
10
3. (8 pts) Simplify the following K-map to get a minimal SOP form.
4. ( 8 pts) Simplify the following K-Map to get a minimal POS form.
5. ( 8 pts) On the diagram below, I want Y to be asserted (LOW TRUE) when both switches are depressed. Draw the Gate(s) that I need. Be sure to list the GATE NUMBERS (i.e. 7400, 7402, etc).
00 01 11 10
00
01
11
10
AB
CD
00 01 11 10
00
01
11
10
6. (8 pts) On the following map, identify a PRIME IMPLICANT, an ESSENTIAL PRIME IMPLICANT, and a NON-ESSENTIAL Prime Implicant.
7. (10 pts) a. I would like to implement one function F (A,B,C) and one function G(W,X,Y,Z) in the same memory device. Note that the two functions do not share any common variables. What size memory device do I need? (specified as K x M, where K is the number of locations, M is the number of bits per location).
b. . I would like to implement the function F (A,B,C), G(B, C, D), and H(C, D,E) in the same memory device. Note that the three functions share some common variables. What size memory device do I need? (specified as K x M, where K is the number of locations, M is the number of bits per location)
8. (5 pts) On the attached PLD diagram (Figure 1), explain what function is implemented according to the fuse marking.
Y’ = ??????
00 01 11 10
00
01
11
10
9. (5 pts) Write the following function in SOP form using the minterms indicated. Do NOT minimize. F(A,B,C,D) =
Σ
m(3,5,15)10. (5 pts) Write the following function in POS form using the maxterms indicated. Do NOT minimize. F(A,B,C,D) =
Π
M(3,5,15)11. (15 pts) For the PLD diagram labeled as "Figure 2", answer the following questions:
a. What is the maximum number of logic equations I could implement in this PLD at the same time?
b. What is maximum number of input variables that equation could have?
c. What is the maximum number of product terms each equation could have? (assuming that an output is NOT fed back around to an input).
d. Show how to implement the equation (do NOT attempt to minimize this equation, implement as shown):
12. Fill in the blanks using terms from the following list:
INEFFICIENT , Volatile, 1, JEDEC, Non-Volatile, 0, VHDL, EFFICIENT, PLD, PRODUCT TERM, Memory, LookUp Table, Intact, Fuse, POS, SOP, Non-Intact
a. When all fuses are intact, the value of a product term in a PAL is ___________________ .
b. A memory is ________________ at implementing wide Boolean functions and multiple functions of independent variables.
c. A __________________ File specifies which fuses should be blown or left intact within a PLD.
d. A PLD which must be reconfigured (reprogrammed) on every power up has ________________ programming.
e. Another name for a memory is _____________________ when it is used to implement a combinational function.
EE 3714 Test #2 - Spring 2000 – Reese
Student ID Number: _______________________ (no names please) Work all problems (13 questions)
1. (8 pts) Plot the following function on a K-Map.
F(A,B,C,D) = ABC' + A'D'
PLOT ONES.
2. ( 8 pts) Plot the following function on a K-Map. F(A,B,C,D) = P M(1,4,5,8,11,14,15)
PLOT ZEROS.
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
00 01 11 10
00
01
11
10
AB
CD
0
0
0
0
0
0
3. (8 pts) Simplify the following K-map to get a minimal SOP form.
F = AC' + B'D
4. ( 8 pts) Simplify the following K-Map to get a minimal POS form. F' = A'D' + A'B + BC + CD'
F = (A+D)(A+B')(B'+C')(C'+D)
5. ( 8 pts) On the diagram below, I want Y to be asserted (LOW TRUE) when either switch is depressed. Draw the Gate(s) that I need. Be sure to list the GATE NUMBERS (i.e. 7400, 7402, etc).
Original Diagram had a low true switch(B) OR'ed with a HIGH TRUE switch (A) to get a low true output..
Need either a 7404 on B switch combined with a 7402 gate. OR a 7404 on A switch combined with a 7408 gate.
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1
00 01 11 10
00
01
11
10
AB
CD
0
0
0
0
0
0
0
0
6. (9 pts) On the following map, identify the following (give the product term): a. PRIME IMPLICANT ___BD_________
b. ESSENTIAL PRIME IMPLICANT ___BD_____________ c. NON-ESSENTIAL Prime Implicant. ____ABC'___________
7. (5 pts) a. What sized memory device (K x M) would be needed to implement your SSN decode lab? F1, F2, F3, F4 each a function of the same four variables (A,B,C,D) 16 x 4
b. (5 pts) What kind of boolean equations is a memory device inefficient at implementing? Functions with many variables, multiple functions that do not share the same variables.
8. (5 pts) On the attached PLD diagram (Figure 1), explain what function is implemented according to the fuse marking? Give the SOP form for Y' !!!!
Y' = A'DJ'E + FG + C'
9. (5 pts) Write the following function in SOP form using the minterms indicated. Do NOT minimize. F(A,B,C,D) =
S
m(2, 7, 11) = A'B'CD' + A'BCD + AB'CD10. (5 pts) Write the following function in POS form using the maxterms indicated. Do NOT minimize. F(A,B,C,D) =
P
M(2, 7, 11) = (A+B+C'+D)(A+B'+C'+D')(A'+B+C'+D')11. a.(5 pts) In class, I made the statement "Minimization is technology dependent". What does this mean? Give an example using the PAL shown in Figure 1.
The PAL has only 4 product terms per output. Does not do any good to minimize an equation to use less than 4 product terms.
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
b. (5 pts) Minimization is aimed at reducing 'resource' usage in an implemenation technology. Name two 'resources' in a PAL that minimization should try to conserve.
INPUTS, OUTPUTS, Product terms (equations must have no more than 4).
12. (8 pts) Plot the following function on the K-MAP shown F(A, B, C, D) = A xor B xor C
Create TRUTH TABLE, then plot on map.
A B C D A xor B xor C 0 0 0 0 0
0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1
13. (8 pts) Minimize the following K-Map to an SOP form: B'D' + ABC'D + A'BCD
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
1
1
1
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1
EE 3714 Test #2 Solutions - Fall 2001 – Reese
Student ID Number: _______________________ (no names please)
Work all problems.
1. (6 pts) Plot the following function on a K-Map.
F(A,B,C,D) = A'B'CD + AC' + BCD'
2. ( 6 pts) Minimize the following K-map to produce a minimal SOP form.
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1 1
1
AC’
BCD’
A’B’CD
00 01 11 10
00
01
11
10
AB
CD
1
1
1
1
1 1
1
AC’
BCD’
A’B’CD
00 01 11 10
00
01
11
10
AB
CD
1
1
1 1
1 1
1
1
0
0
0 0
0
0 0
0
F = A’B’C’D’ + A’BD +ABD’+ CD
00 01 11 10
00
01
11
10
AB
CD
1
1
1 1
1 1
1
1
0
0
0 0
0
0 0
0
3. (6 pts) Simplify the following K-map to get a minimal POS form.
4. (6 pts) On the following map, identify the following (give the product term) for a minimal SOP equation:
a. ESSENTIAL Prime Implicant C’D or AC
b. NON-ESSENTIAL Prime Implicant. AD
Remember that a PI cannot be combined with another group, and a non-essential PI does not have to be included in the minimal equation. AD is a non-enssential PI because all of its ‘1’s are covered by other PI groupings.
00 01 11 10
00
01
11
10
AB
CD
1
0
1 0
0 0
0
0
1
0
0 0
1
1
1
0
F’ = A’B’D + BC’ + AC
F = (A+B+D’)(B’+C)(A’+C’)
00 01 11 10
00
01
11
10
AB
CD
1
0
1 0
0 0
0
0
1
0
0 0
1
1
1
0
F’ = A’B’D + BC’ + AC
F = (A+B+D’)(B’+C)(A’+C’)
00 01 11 10
00
01
11
10
AB
CD
0
1
0
1
0 1
0
1
0
0
1
1
1
0
0
1
Essential PI: C’D
Essential PI: AC
Non-Essential PI: AD
00 01 11 10
00
01
11
10
AB
CD
0
1
0
1
0 1
0
1
0
0
1
1
1
0
0
1
Essential PI: C’D
5. (6 pts) I would like to implement the functions 'F', 'G' below in one or more memory devices. Note that F, G share some variables (inputs 'A', 'B' are common to both F, G).
F(A,B,C) = AB +CA + CB
G(A,B, D, E) = A + B + D'E'
a. What sized memory (K x M) would be needed to implement both F and G in ONE MEMORY chip? 32 x 2 (25 x 2) --- There are 5 common variables, 2 outputs.
b. What sized memory (KxM) would be needed to implement only equation 'F'?
8 x 1 (23 x 1) There are 3 variables, 1 output.
6. (10 pts) Fill in the blanks using terms from the following list:
INEFFICIENT , Volatile, 1, JEDEC, Non-Volatile, 0, VHDL, tri-state buffer, EFFICIENT, PLD, PRODUCT TERM, Memory, Intact, Fuse, POS, SOP, Non-Intact
i) When all fuses are blown, the value of a product term in a PAL is ONE (a blown fuse leaves its input as a ‘1’ value, all ‘1’s to a product term produces a ‘1’).
ii) A _PLD_ is efficient at implementing wide Boolean functions and multiple functions of independent variables.
iii) A programmable logic device is ___non-volatile______ if it retains its programming on power down.
iv) A __tri-state buffer_________ has three output states: '1', '0' and high impedance.
v) __VHDL_____ is a language used for specifying boolean equations which can be mapped to programmable logic.
7. (6 pts) Show via a schematic how the 2/1mux equation Y = I0 S' + I1 S can be implemented using tri-state buffers.
I0
Y
I1
S
I0
Y
8. (8 pts) The symbol on the left is for a one-bit 2/1 mux. The symbol on the right is for a one bit 4/1 mux. Draw a schematic showing how to create the 4/1 mux using 2/1 muxes.
9. (6 pts) The symbol below is for a 2 to 4 decoder. Show the gating necessary to implement the Y2 output.
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S[1..0]
I2
I3
2
I0
I1
Y
S[1..0]
I2
I3
2
Y0
Y1
Y2
Y3
S[1..0]
2
Y0
Y1
Y2
Y3
S[1..0]
2
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
S0
I0
I1
I2
I3
S1
Y
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
S0
I0
I1
I2
I3
S1
Y
S0
S1
Y2
Y2 = S1 S0’
Y2 = 1 when S = 10
S0
S1
Y2
Y2 = S1 S0’
Y2 = 1 when S = 10
10. (8 pts) For the device shown below, fill in the VOLTAGE truth table for the inputs. Use 'L', 'H' for level inputs. For a rising edge needed on an input pin, use "L→ H", for a falling edge needed use "H→L".
Inputs Output result
C D S R
Force output to a L
regardless of clock X X H L
Force output to a H regardless of clock
X X L H
Set output to a H on next active clock edge
L→ H H H H
Set output to a L on next active clock edge
L→ H L H H
Set, Reset are NEVER don’t care inputs. They always affect the DFF.
11. (6 pts) Complete the timing diagram below for the device shown:
12. ( 6 pts) Draw the schematic for a rising edge triggered DFF using two D-latches.
D
Q
C
S
R
D
Q
C
S
R
D
G
Q
G D Qlatch holds latch transparent latch holds
D=1
Q last value is 1
G
D
Q
latch holds latch transparent latch holds
D=1
13. (6 pts) Draw the gate schematic for a Set/Reset latch with LOW TRUE INPUTS.
14. (5 pts) A clock has a period of 40 ns (1 ns = 10-9 s). What is the clock frequency in Mhz (1 Mhz
= 106 Hz)
Clock freq = 1 /(40 x 10-9) = 0.025 x 109 = 25 x 106 = 25 MHz
15. (3 pts) For the device shown in problem 10, what input(s) have a setup/hold associated with it?
Only input D has a setup and hold time associated with it. Input D has satisfy setup/hold times in relation to the rising clock edge in order for correct operation.
16. (6 pts) For the device shown in problem 10, what input(s) have a propagation delay associated with them?
Inputs C, S, R have propagation delays – changes on these inputs can cause the output to change.
R
S
Q
Q’
R
S
Q
EE 3714 Test #3 Solution - Fall 2001 – Reese
Work all problems.
1. (15 pts) For the ASM chart shown below, the state encoding is one-hot using S0=001, S1=010, S2=100.
a. Write the boolean equation for the D1 input (D input for state S1 D-Flip-flop)
D1 = Q0 N M + Q2 M
b. Write the boolean equation for the "Sh" output. Sh = Q0 N M’ + Q1 + Q2 M’
2. ( 15 pts) For the ASM chart in Figure #1, complete the timing diagram below for the State and "Sh" waveforms. Assume that rising edge triggered DFFs are used for the FSM implementation. Make sure you complete the waveforms for State, Ad through the last clock cycle.
CLK
S0
State
N
M
K
0
0
0
Sh
???
Reset
Reset to S0
S1
S2
S1
S2
CLK
S0
State
N
M
K
0
0
0
Sh
???
Reset
Reset to S0
3. (20 pts) For the counter shown below, give the control input values needed for the operations listed in the table. For input values, use the symbols X (don’t care), ‘H’ (high), ‘L’ (low) and ↑ (rising edge).
Operation CLK ACLR LD DIR EN
HOLD (Y = Yold)
X or
↑L
L
X
L
LOAD (Y = Din)
↑L H X X
Increment (Y=Yold+1)
↑L L L H
Decrement (Y=Yold-1)
↑L L H H
Asynchronous Clear
X
H
X
X
X
4. (20 pts) The ASM chart below specifies the behavior for the FSM that is controlling the counter that is shown. On the timing diagram, fill out the waveforms for the State, ld, en, and Q values given the Start and D values shown. Draw the waveforms through state S2 of the ASM. Assume the counter and FSM are rising edge trigerred.
CLK
$ 40
$ 50
$ 60
$70
$ 90
$ 08
$ 04
D
Start
Start?
S0
S1
S2
0
1
ASM
ld
en
en
ld
D
Q
8
8
Q[7:0]
D[7:0]
FSM
Clk
Clk
ld
start
en
sclr
en
sclr
State
S0
ld
en
Q
S1
S2
??
??
$40
$40
$41
$42
$42
CLK
$ 40
$ 50
$ 60
$70
$ 90
$ 08
$ 04
D
Start
Start?
S0
S1
S2
0
1
ASM
ld
en
en
Start?
S0
S1
S2
0
1
ASM
ld
en
en
ld
D
Q
8
8
Q[7:0]
D[7:0]
FSM
Clk
Clk
ld
start
en
sclr
en
sclr
ld
D
Q
8
8
Q[7:0]
D[7:0]
FSM
Clk
Clk
ld
start
en
sclr
en
sclr
State
S0
ld
en
Q
S1
S2
??
5. (10 pts) For the counter below, add a SYNCHRONOUS CLEAR capability that takes precedence over the other control lines.
6. (10 pts) a. For the ASM chart in problem #1, list the states in which output Sh is a ‘conditional’ output.
States S0, S2 (Sh in oval circles)
b. For the ASM chart in problem #1, list the states in which output Sh is an ‘unconditional’ output.
State S1
EN
ACLR
D
N
N
R
DFF
0
1
S
Y
EN
DIN
LD
CLK
N
N
DIN
Y
Incre menter
Q
EN
DIN
Y
Decrementer
1
0
S
Y
DIR
Up/down counter
N
N
N
N
Y
SCLR
Added this for sclr
EN
ACLR
D
N
N
R
DFF
0
1
S
Y
EN
DIN
LD
CLK
N
N
DIN
Y
Incre menter
Q
EN
DIN
Y
Decrementer
1
0
S
Y
DIR
Up/down counter
N
N
N
N
Y
SCLR
EN
ACLR
D
N
N
R
DFF
0
1
S
Y
0
1
S
Y
EN
DIN
LD
CLK
N
N
DIN
Y
Incre menter
Q
EN
DIN
Y
Decrementer
1
0
S
Y
1
0
S
Y
DIR
Up/down counter
N
N
N
N
Y
SCLR
7. (10 pts) Show the gating that will implement the high level VHDL statement below (CNT is a 3 bit bus):
Y <= ‘1’ when (CNT = “011” or CNT = “101”) else ‘0’;
Y = CNT2’ CNT1 CNT0 + CNT2 CNT1’ CNT0
Y
Cnt2’
Cnt1
Cnt0
Cnt2
Cnt1’
Cnt0
Y
Cnt2’
EE 3714 Test #3 - Fall 1999 – Reese
SSN: _______________________ (no names please) Work all problems.
1. (5 pts) Identify the following device. What values do the inputs have to be for the outputs to have the following values Y0= 0, Y1= 0, Y2= 1, Y3=0.
2. ( 8 pts)Assume that the initial state device shown below is a '0'. Draw a timing diagram that will cause the state of the device to be changed to '1'.
Y0
Y1
Y2
Y3
EN
S
2
S
3. (8 pts) Complete the timing diagram below for the Q output of the device that is shown.
4. (8 pts ) Complete the timing diagram below for the Q output of the device that is shown.
D
G
Q
G
D
Q
D
C
Q
C
D
5. (8 pts) Complete the timing diagram below for the Q output of the device that is shown.
6. For a flip-flop of your choosing (D, J-K, T) , draw a timing diagram and illustrate setup and hold time constraints.
7. (5 pts) What is the clock period of a 50 Mhz clock (1 Mhz = 106)
J
C
Q
K
C
J
8. (5 pts) What is the value of $A3 shifted to the right by one position with the serial input bit = ‘1’?
9. (5 pts) How is an asynchronous input different from a synchronous input?
10. Draw the schematic for a 1-bit register. The inputs are CLK, D,LD. The output is Q. The LD input ais high true.
12. (10 pts) Draw a schematic for a 3- bit counter that has a parallel load. Use a three bit incrementer combinational logic block as one of your building blocks (the incrementer has a 3-bit input A[2..0], a one bit input EN, a three bit output Y[2..0]. When EN=1, then Y= A+1; when EN=0, then Y=A). The inputs to the counter is CLK, DIN[2..0], LD, EN. The output is DOUT[2..0]. The LD, EN inputs are high true. (You do not have to show the internals of the incrementer block).
EE 3714 Test #3 - Fall 1999 Solutions
1. (5 pts) Identify the following device. What values do the inputs have to be for the outputs to have the following values Y0= 0, Y1= 0, Y2= 1, Y3=0.
2. ( 8 pts)Assume that the initial state device shown below is a '0'. Draw a timing diagram that will cause the state of the device to be changed to '1'.
3. (8 pts) Complete the timing diagram below for the Q output of the device that is shown.
4. (8 pts ) Complete the timing diagram below for the Q output of the device that is shown. D G Q D C Q
2 to 4 Decoder with Enable
Need S1= 1, S0= 0, EN = 1.
S R Q Y0 Y1 Y2 Y3 EN S 2 G D Q
latch holds latch transparent latch holds
D=1
Q last value is 1
G
D
Q
latch holds latch transparent latch holds
D=1
Q last value is 1
C
D
Q
D = 1
Q = 1
Rising edge triggered DFF C
D
Q
D = 1
Q = 1
Rising edge triggered DFF S
R
Q
R=1
SR latch with low true inputs Set operation S
R
Q
R=1
5. (8 pts) Complete the timing diagram below for the Q output of the device that is shown.
6. For a flip-flop of your choosing (D, J-K, T) , draw a timing diagram and illustrate setup and hold time
constraints. SEE NOTES ON SETUP/HOLD for DFF.
7. (5 pts) What is the clock period of a 50 Mhz clock (1 Mhz = 106)
Period = 1/ Frequency = 1/ (50 x 106) = 0.02 x 10-6 = 20 x 10-9 = 20 ns
8. (5 pts) What is the value of $A3 shifted to the right by one position with the serial input bit = ‘1’? $A3 = 1 0 1 0 0 0 1 1
Right Shifted value: 1 1 0 1 0 0 0 1 = $D1
9. (5 pts) How is an asynchronous input different from a synchronous input?
Asynchronous inputs are independent of clock, synchronous inputs effect circuit only on active clock edge.
10. Draw the schematic for a 1-bit register. The inputs are CLK, D,LD. The output is Q. The LD input
ais high true. SEE NOTES.
11. Draw the diagram of a rising edge trigerred D-FF using D Latches. SEE NOTES (the inverted clock
goes to the FIRST D latch, the master latch).
12. (10 pts) Draw a schematic for a 3- bit counter.… etc.
SEE NOTES.
13. (10 pts) Draw the schematic of a 4-1 mux using Tri-state buffers. You can use an decoder block in your design, and you do not have to show the internal details of the decoder.
SEE NOTES. J C Q K
C
J
Q
K
Falling edge triggered JK.
J = 1
K = 0
Q is
set
J = 1
K = 1
Q is
toggled
J = 0
K = 0
Q holds
C
J
Q
K
Falling edge triggered JK.
J = 1
K = 0
Q is
set
J = 1
K = 1
Q is
toggled
J = 0
K = 0
EE 3714 Test #3 Solutions- Spring 2000 – Reese Work all problems.
1. (6 pts) Draw the schematic of a 2/1 mux using only combinational gates.
2. (6 pts) Draw the schematic of a 2/1 mux using tri-state buffers plus combinational gates.
3. (8 pts) The symbol on the left is for a one-bit 2/1 mux. The symbol on the right is for a three bit 2/1 mux. Draw a schematic showing how to create the three bit 2/1 mux using the one-bit 2/1 mux.
I0
I1
Y
S
I0
I1
Y
S
A[2:0]
B[2:0]
D[2:0]
I0
S’
I1
S
Y
A
Y
B
S
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
A0
B0
A1
B1
A2
B2
Y0
Y1
4. ( 8 pts)Assume that the initial state device shown below is a ’0’. Complete the timing diagram below for the Q output.
5. (8 pts) Draw the schematic for a falling edge-triggered D-FF using D latches.
6. (8 pts ) Draw the gate level schematic for an SR latch, either with high true inputs or low true inputs. Indicate if your SR inputs are high or low true. (you will not get credit if you indicate that you have an SR with low true inputs, yet your gate level implementation is for high true inputs, or vice-versa).
D
Q
C
S
R
C
D input
R
S
Q
D
Q
G
Q’
D
Q
G
Q’
D
C
Q
Ds
Cs
R
S
Q
Q’
S
Q
R
Q’
7. (8 pts) For the device shown below, indicate what type of TIMINGS might be found in the datasheet for the following inputs (circle ONE OR MORE timing for each input).
Correct Choices shown in BOLD.
a. D input TPLH TPHL Setup Hold b. C input TPLH TPHL Setup Hold c. S input TPLH TPHL Setup Hold d. R input TPLH TPHL Setup Hold
D input only has setup/hold, no prop delay because it is clock edge that triggers change on Q output, not change on D input. C input can cause Q to go to either ’1’ or ’0’, so has both TPLH and TPHL. S input can only change Q to 1, so only TPLH. R input can only cause Q to go to ’0’, so only TPHL.
8. (5 pts) Given a clock period of 5 ns, what is the clock FREQUENCY in MHz!!!!!! Freq = 1/(5 x 10-9) = 0.2 x 109 = 200 x 106 = 200 MHz
9. (5 pts) What is the value of $54 shifted to the LEFT by one position with the serial input bit = ‘1’? $54 = 0 1 0 1 0 1 0 0 SIN(1)
left shift 1 0 1 0 1 0 0 1 = $A9
D
Q
C
S
10. (10 pts)Draw the schematic for a 3 bit RIGHT shift combinational logic block built using 2/1 muxes. The 3 bit left shifter will do the following:
When EN = 0, Y[2:0] = A[2:0]
When EN = 1, Y = A RIGHT shifted by 1, serial input bit is ’SIN’.
11. (8 pts) Illustrate via a timing diagram the DIFFERENCE between a D-latch and a D-FF.
12. (5 pts) Fill in the following truth table for a J-K FF (rising-edge triggered) CLK J K PS (Q) NS (Q+)
↑ 0 0 Q Q (hold) ↑ 0 1 Q 0 (reset) ↑ 1 0 Q 1 (set) ↑ 1 1 Q Q’ (toggle)
13. (5 pts) Fill in the following truth table for a Toggle (T) FF (rising-edge triggered) CLK T PS (Q) NS (Q+)
↑ 0 Q Q (hold) ↑ 1 Q Q’ (toggle)
I0
I1
Y
S
I0
I1
Y
S
I0
I1
Y
S
A0
A1
A1
A2
A2
SIN
Y0
Y1
Y2
EN
Y2Y1Y0 = A2A1A0 when EN=0
Y2Y1Y0 = SINA2A1 when EN=1
D
C
Q (DFF, falling edge triggered)
14. (10 pts) The schematic below shows a count-up counter with a load and synchronous clear capability.
The following table lists all 8 combinations of the three control lines: LD, EN, SCLR. Besides each combination of LD, EN, SCLR, describe what the new value of the counter will be:
a. KEEP old value b. INC old value by 1 c. DIN (load din)
d. DIN + 1 (load DIN + 1) e. 0 (clear register) f. 1 (load a ’1’ into register)
Put something for EVERY combination.
LD EN SCLR ACTION 0 0 0 Keep Old Value 0 0 1 0 (clear register) 0 1 0 INC old vlaue by 1 0 1 1 1 (load a ’1’ into register) 1 0 0 DIN (load din)
1 0 1 DIN (load din) 1 1 0 DIN (load din) 1 1 1 DIN (load din)
D
N
N
R
DFF
0
1
S
Y
EN
DIN
LD
CLK
N
N
DIN
Y
Incrementer
Q
N
SCLR
EE 3714 Test #4 - Fall 1999 – Reese
SSN: _______________________ (no names please) Work all problems.
1. (10 pts) For the ASM chart in Figure #1 (pg 586, book, prob 22.17), the state encoding is one-hot using S0=001, S1=010, S2=100.
a. Write the boolean equation for the D2 input (D input for state S2 D-Flip-flop)
b. Write the boolean equation for the Z1 output.
2. ( 15 pts) For the ASM chart in Figure #1, complete the timing diagram below for the State and Z1 waveforms. Assume that rising edge triggered DFFs are used for the FSM implementation. Make sure you complete the waveforms for State, Z1 through the last clock cycle. A
3. (10 pts) Refer to the Figure 2 Datapath. Give the value of the counter at the end of state S2 for each of the ASM charts in Figure 2 ASM Charts. You can assume the FSM is in state S0 at the beginning of the timing diagram in Figure 2 Datapath.
a. ASM Chart a
b. ASM Chart b
CLK
S0
State
X1
X2
X3
0
0
0
Z1????
S1
S1
S2
S1
?????
Reset
4. (10 pts).
Draw a tree network using 2-input AND gates that will perform an AND of 8 inputs (A,B,C,D,E,F,G,H). Give the maximum propagation delay if the delay of each gate is 1 ns.
5. (10 pts) Draw the block diagram of an 8-bit adder/subtractor using an 8-bit adder as a building block.
7. (10 pts) Below is an iterative network that does equality comparison of two four bit values. Draw the logic that is inside one of the cells (Y <= ‘1’ when (A = B) else ‘0’);
8. (5 pts) Give me a boolean equation that implements the following VHDL statement Y <= A when (S = ‘0’) else not (B);
9. (5 pts) One of the Dice game blocks had an output called “D2312”. This output was true whenever the four bit input SUM was equal to 2, 3, or 12. Give me a boolean equation that implements this.
10. (5 pts) Given a 12 state FSM:
a. How many FFs do I need if I use one-hot encoding?
b. How many FFs do I need if I use binary count order encoding? c. How many FFs do I need if I use Grey code encoding?
11. ( 5 pts) If I have an FPGA that needs to be configured each time it is powered up, what is being used as the primitive logic element?
12. ( 5 pts) What is a requirement for the block that is used as the primitive logic element in an FPGA?
A
Y
B
P
A(0)
B(0)
1
A
Y
B
P
A(1)
B(1)
A
Y
B
P
A(2)
B(2)
EE 3714 Test #4 Solutions Fall 99 Work all problems.
1. (10 pts) For the ASM chart in Figure #1, the state encoding is one-hot using S0=001, S1=010, S2=100. (see Figure for problem 22.17, pg 586, in book)
a. Write the boolean equation for the D2 input (D input for state S2 D-Flip-flop) D2 = Q2 X2 + Q0 X1’ X2 + Q0 X1 X2 X3
b. Write the boolean equation for the Z1 output. Z1 = Q0 X2 + Q1 + Q2
( 15 pts) For the ASM chart in Figure #1, complete the timing diagram below for the State and Z1 waveforms. Assume that rising edge triggered DFFs are used for the FSM implementation. Make sure you complete the waveforms for State, Z1 through the last clock cycle.
2. (10 pts) Refer to the Figure 2 Datapath. Give the value of the counter at the end of state S2 for each of the ASM charts in Figure 2 ASM Charts. You can assume the FSM is in state S0 at the beginning of the timing diagram in Figure 2 Datapath.
a. ASM Chart a: $46 b. ASM Chart b $28
3. (10 pts).
Draw a tree network using 2-input AND gates that will perform an AND of 8 inputs (A,B,C,D,E,F,G,H). Give the maximum propagation delay if the delay of each gate is 1 ns. See Notes
4. (10 pts) Draw the block diagram of an 8-bit adder/subtractor using an 8-bit adder as a building block. See Notes
S0
State
X1
X2
X3
0
0
0
Z1
S1
S1
S2
S1
0
?????
Reset
5. (10 pts) Draw the ASM chart for a modulo three counter (will count “00”, “01”, “10”, “00”, “01”, ..etc) when EN=1. If EN=0, then the counter will hold its value.
See Notes
6. (10 pts) Below is an iterative network that does equality comparison of two four bit values. Draw the logic that is inside one of the cells (Y <= ‘1’ when (A = B) else ‘0’);
7. (5 pts) Give me a boolean equation that implements the following VHDL statement Y <= A when (S = ‘0’) else not (B);
Y = A S’ + B’ S’
8. (5 pts) One of the Dice game blocks had an output called “D2312”. This output was true whenever the four bit input SUM was equal to 2, 3, or 12. Give me a boolean equation that implements this.
D2312 <= S3’S2’S1S0 + S3’S2’S1S0 + S3 S2 S1’ S0’ 9. (5 pts) Given a 12 state FSM:
a. How many FFs do I need if I use one-hot encoding? 12
b. How many FFs do I need if I use binary count order encoding? 4 c. How many FFs do I need if I use Grey code encoding? 4
10. ( 5 pts) If I have an FPGA that needs to be configured each time it is powered up, what is being used as the primitive logic element? LOOKUP TABLE
11. ( 5 pts) What is a requirement for the block that is used as the primitive logic element in an FPGA? It must be a complete logic family.
A
Y
B
P
A(0)
B(0)
1
A
Y
B
P
A(1)
B(1)
A
Y
B
P
A(2)
B(2)
A
Y
B
P
A(3)
B(3)
A B
EE 3714 Test #4 Solutions- Spring 2000 – Reese Work all problems.
1. (15 pts) For the ASM chart in Figure #1 (Figure 22-10, pg 575, book), the state encoding is one-hot using S0=001, S1=010, S2=100.
a. Write the boolean equation for the D2 input (D input for state S2 D-Flip-flop) D2 = Q0 N M’ + Q2 M’ K’ + Q1 K’
b. Write the boolean equation for the "Ad" output. Ad = Q2 M + Q0 N M
2. ( 15 pts) For the ASM chart in Figure #1, complete the timing diagram below for the State and "Ad" waveforms. Assume that rising edge triggered DFFs are used for the FSM implementation. Make sure you complete the waveforms for State, Ad through the last clock cycle.
CLK
S0
State
N
M
K
0
0
0
Ad
???
Reset
Reset to S0
S2
S1
S2
S1
N=1, M=0
M=1
K=0
M=1
3. (20 pts) Refer to the ASM chart shown below:
Assume the implementation uses one D-FF, and the state encoding is S0=0, S1=1. Complete the state table below, and draw the implementation of this digital system (show the DFF plus combinational gates that implement the ASM chart. Use an asychronous reset in your design to reset to state S0.
PS A B NS
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
D = AB + QB + QA
A?
S0
S1
0
1
B?
0
1
A?
1
B?
0
1
0
C-Element
PS(Q)
1
0
0
0
1
00
AB
0
1
1
0
1
01
11
10
DFF D Q
C R B
Clk
Reset
NS (D)
4. (10 pts).
Draw the gate level diagram of a 4-bit comparator circuit (Eq <= ’1’ when (A = B) else ’0’).
5. (15 pts) The schematic below shows a sequential system with a 2-bit binary counter. Complete the timing diagram below for the Q output and ’clk_en’ signals. The EN input to the counter enables counting, the SCLR input is a synchronous clear. The counter is rising edge triggered.
Q
2
Q[1:0]]
Clk
Clk
en
sclr
Q0
Q1
sclr
en
clk_en
A3 B3
A2 B2 A1 B1 A0 B0
xnor xnor xnor
EQ xnor
CLK
00
Q[1:0]
Sclr
Clk_en
En
01
10
11
6. (10 pts) Explain the difference between a complex PLD and an Field Programmable Gate Array. Draw diagrams to illustrate the difference.
See notes for diagram. A Complex PLD has several PAL blocks with programmable routing between the blocks. An FPGA has a row-column arrangement of primitive logic element (anything that can implement a complete logic family like a 2-input Nand gate or 4 input lookup table) with programmable routing between the elements.
7. (5 pts) Discuss two advantages for describing a circuit via VHDL rather than a schematic of gates. VHDL is more readable in terms of circuit behavior than a schematic, is easier to change, is more portable between different implementation techologies.
8. (5 pts) What common combinational building block does the following VHDL statement describe?? Y <= A when (s = 1) else B
This is a 2-to-1 mux .
9. (5 pts) A sequential system can be broken into two parts-- combinational logic + memory. We also talked about dividing a sequential system into two parts by FUNCTION -- what was the terms we used for these functional parts of a sequential system???
1
BR 1/99 1
Start? S0 S1 S2 0 1 FSM Fig 2a
ld
en
CLK
Cntr
$ 45 $ 27 $ 30 $ 35 $ 51 $ 83 $24 $ 02
D Start Ld En $ 45 ?? S0 State $ 46
S1 S2 ??
ld D Q 8 8 Q[7:0] D[7:0]
FSM
Clk Clk ld start en sclr en sclrBR 1/99 2
CLK
$ 45 $ 27 $ 30 $ 35 $ 51 $ 83 $24 $ 02
D Start Ld En $ 45 ?? S0 $ 28
S1 S2 ??
Start? S0 S1 S2 0 1 FSM Fig 2b
2
BR 1/99 3
CLK
S0 State
X1
X2
X3 0 0
0
Z1
S1 S1 S2 S1
0 ?????
Reset
Reset forces state to S0 initially.
BR 1/99 4
CLK
S0 State
X1
X2
X3 0 0
0
Z1????
S1 S1 S2 S1
?????
Reset
