Multiple stage amplifiers

Multiple stage amplifiers

Aims:

•

Examine a few common 2-transistor amplifiers:

-- Differential amplifiers

-- Cascode amplifiers

-- Darlington pairs

-- current mirrors

Two stage BJT amplifiers

Comments

High Voltage gain High bandwidth High Zin lowZout

Higher Zout than CB/CG

Second stage to improve on CB/CG Not common

Instead of CE, offers higher Zin

High voltage gain and bandwidth High current gain

BJT Name 1st Stg 2nd Stg (voltage amp) CE CE cascode CE CB (op-amp) CE CC (current buffer) CB CE (current buffer) CB CB (Not common) CB CC (Not common) CC CE differential amp CC CB darlington CC CC

We study them separately because they very often appear as building blocks.

There are 9 possible cascades

of 2 single stage transistor amplifiers.

Differential amplifier

•

Half circuit (i.e. driven from one side) is CC followed by CB

•

Very wide frequency response

Cascode amplifier

• Wideband voltage amplifier

• CE stage operates at gain=-1, minimising miller loading of input.

• CB gives all the voltage gain, acting as transimpedance of value Z_L

• The cascode has a much higher output impedance (other than Z_L) than the CE amplifier (the common emitter Early resistance acts as series-series feedback to the common base with loop gain =g_mR_CE)

Darlington pair

• The darlington pair is a high gain power amplifier it has:

– Unity voltage gain

– High current gain equal to the product of the two transistor current gains • Often used as a single transistor for higher beta. But :

• has high input DC voltage drop

• Good frequency response due to the absence of shunt Miller feedback.

• However, series Miller feedback introduces tendency for instability when driving capacitive loads.

Current mirrors

• Use one transistor with unity feedback as a transimpedance amplifier to measure the V_BE required for a given current.

• Use a second transistor as transconductor to create a copy of the input current

• Can make a current amplifier by using larger output transistor.

• Current gain is in error due to base currents (i.e finite current gain)

• No DC gain error in FET mirrors (remember the AC current gain of a FET scales as the inverse of frequency!)

• Main source of error transistor mismatch

– “V_BE mismatch at a constant current” (BJT) – V_T mismatch in FET

• AC analysis as in CE amplifier with extra source admittance due to input transistor

• Current mirrors are used for DC biasing multi-stage amplifiers

• Current mirrors often used load to a differential amplifier to turn the differential amplifier into a differential transconductor.

Improved current mirrors

The Wilson Mirror

has high output Z, since output

stage is a cascode amplifier

The buffered mirror

The CC amplifier feeding the bases

reduces current gain error

Scaling Mirrors: The Widlar mirror

• The Widlar scaling mirror is often used as fixed scaling current source (a)

• Can be made as a buffered or a Wilson source (c)

• A feedback resistor can be added on the input side turning it into a transconductor (b)

• A base resistor as shown can provide “beta compensation” (i.e. introduce a zero in the frequency response (c)

(a)

_(b)

Some more mirrors

(a)

(a) Buffered Widlar mirror

(b) The “gm-compensated” mirror

Current mirror as a differential amp load

• The current mirror maps the left side current differential into the right side.

• The large signal response of this circuit is V_out=tanh(V₊-V_-)

• This circuit (a 3 stage amplifier! Why?)

• This circuit It has extremely high voltage gain: A_V is of the order of V_A/V_th

• This circuit is also used for mixers if a

transconductor is used in the place of the tail current source.

• There is no Miller effect on the left half circuit

• If this circuit drives a current sink at the output there is no Miller effect on the right half circuit either!

• The diff-amp has an extremely wide frequency response. This is partly a consequence of the resistive impedance match between the output of the first stage (emitter of Q1)and input of the

second stage (emitter of Q2).

Two stage FET amplifiers

F E T C o m m e n t s 1 s t S t g 2 n d S t g C S C S H ig h V o l t a g e g a in C S C G H ig h b a n d w id t h C S C D H ig h Zin l o w Zo u t C G C S H ig h e r Zo u t t h a n C B / C G C G C G S e c o n d s t a g e t o im p r o ve o n C B / C G C G C D N o t c o m m o n N a m e ( vo l t a g e a m p ) c a s c o d e ( o p - a m p ) ( c u r r e n t b u f f e r ) ( c u r r e n t b u f f e r ) ( N o t c o m m o n )

• The analogy we observed between single stage BJT and FET amplifiers applies, to two stage amplifiers. The correspondence is, as before, EÆS, BÆG, CÆD. • The behaviour of BJT and FET configurations is very similar, except for the

difference on the input side of the small signal equivalent circuit.

• A very useful possibility opens up: Use a FET for one stage and a BJT for the other. Mixed bipolar-FET two-stage combinations try to exploit the smaller input admittance of FETs and the better frequency response and power handling

capability of bipolars at the same time.

• This approach gives rise to the “BiCMOS” manufacturing technologies which use FETs for input stages and BJTs for output stages, especially line drivers.

Multistage amplifiers

Vs Rs RIN1 - + -A1 V1 ROUT1 RIN2 + -A2 V2 RO2 RL V1 V2

Source Amp1 Amp2 Load

VL

• Multistage amplifiers are difficult to compute if the components are not unilateral.

• For unilateral amplifiers things are simple. We multiply gains with appropriate

voltage dividers.

• For non-unilateral amplifiers:

• The input impedance of each stage depends on the input impedance of the

next stage

• The output impedance of each stage depends on the output impedance of

the preceding stage.

• This problem has a solution but involves the solution of sets of simultaneous

{

}

1 2 1 1 2 2

1

1

1

1

,

,

1,

2,

1

1

1

L x s s in out in o L x

V

A

A

Y

x

in in

L

V

=

+

R Y

+

R

Y

+

R Y

=

R

∈

Input - output impedance of a loaded amplifier

• We calculate the input impedance of a voltage amplifier driving a load Z_L :

• A similar calculation for the output impedance of a voltage amplifier driven by a finite impedance Thevenin source Z_S gives:

(

)

1 11 1 12 2 1 11 1 12 2 2 21 1 22 2 2 21 1 22 2 2 2 12 2 11 1 1 _{1 22} 22 2 21 1 1 11

1

1

L L L L _L in L g L

i

g v

g i

i

g v

g Y v

v

g v

g i

v

g v

g Y v

i

v Y

g v Y

g v

i

_v

_{g Y}

Z

g Y v

g v

i

g

Y

=

+

⎫

=

−

⎫

⎪

=

+

_⎬

⇒

_⎬

⇒

=

−

_⎭

⎪

= −

_⎭

=

−

⎫

_{⎪ ⇒ = =}

₊

⎬

+

=

_⎪⎭

+ Δ

(

)

(

)

1 11 1 12 2 1 11 1 12 2 2 21 1 22 2 2 21 1 22 2 1 1 s S s S s S

i

g v

g i

i

g

v

i Z

g i

v

g v

g i

v

g

v

i Z

g i

v

v

i Z

=

+

⎫

₌

₋

₊

_⎫

⎪

⎪

=

+

_⎬

⇒

_⎬

⇒

=

−

+

_⎪

⎪

⎭

= −

_⎭

Gain of a fully loaded voltage amplifier

1 11 1 12 2 2 21 1 22 2 1 1 2 2 s s L

i

g v

g i

v

g v

g i

v

v

i Z

i

v Y

=

+

=

+

= −

= −

We start with the amplifier definition, plus the source-load boundary conditions:

After some algebra we conclude that:

G₁₂i₂ i₁ v₁ G11 v2 i₂ G₂₁V₁ G₂₂ Z_S Y_L V_S

(

)(

)

2 21 21 11 22 21 12 11 22 12 21 11 22

,

1

1

1

g s s L s L S L g L s

v

g

g

g g

g g

v

=

+

g Z

+

g Y

−

g g Z Y

=

+

g Z

+

g Y

+ Δ

Y Z

Δ =

−

In a cascade connection,

• V

₁

of network X

₂

= V

₂

of network X

₁

• I

₁

of network X

₂

= -I

₂

of network X

₁

We can define a new set of parameters so that we have a simple way to

calculate the response of cascades of amplifiers.

A suitable definition is:

Cascade connection: Transmission Parameters

X₁ X₂ X₃=X₁X₂ 1 2 1 2

v

A

B

v

i

C

D

i

⎡ ⎤

⎡

⎤

⎡

⎤

=

⎢ ⎥

⎢

_{⎥ −}

⎢

⎥

⎣

⎦

⎣ ⎦

⎣

⎦

With this definition, the ABCD parameters of a cascade of two networks are

found from the matrix product of the individual ABCD matrices ports labelled for

clarity):

₁

₂

₃

₁

₃

1 1 1 2

v

A

B

v

i

C

D

i

_v

_A

_B

_A

_B

_v

_v

_A

_B

_v

⎫

⎡ ⎤ ⎡

⎤ ⎡

⎤

=

_⎪

⎢ ⎥ ⎢

⎥ ⎢

₋

⎥

_{⎡ ⎤ ⎡}

_{⎤ ⎡}

_⎤

_⎡

_⎤

_{⎡ ⎤}

_⎡

_{⎤ ⎡}

_⎤

⎣ ⎦ ⎣

⎦ ⎣

_{⎦ ⎪ ⇒}

Transmission (or ABCD) parameters (2)

2 2 2 2 1 1 2 ₀ 21 2 ₀ 21 1 2 1 2 _{1 1} 2 ₀ 21 2 ₀ 21

1

1

B=

1

1

D=

i v i v

v

v

A

v

G

i

Y

v

A

B

v

i

C

D

i

_i

_i

C

v

Z

i

H

= = = =

∂

−∂

−

=

=

=

∂

∂

⎡ ⎤

⎡

⎤

⎡

⎤

=

⎢ ⎥

⎢

_{⎥ −}

⎢

⎥

∂

−∂

−

⎣

⎦

⎣ ⎦

⎣

⎦

₌

₌

₌

∂

∂

The transmission matrix elements are related to the 4 gains:

A cascade of 2 amplifiers has gains:

1 1 2 2 1 2 1 2 1 2 1 2 1 1 2 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1

1

1

1

1

1

1

1

1

f f f f f f f f f f f f f f f f f f f f f f f f f f f f f

A

B

A

B

A A

B C

A B

B D

A

B

C

D

C

D

C A

D C

C B

D D

C

D

g g

y z

g y y h

g

y

y z

g g

y h

g y

g g

y z

g y

y h

z g h

z

z g

h z

+

+

⎡

⎤ ⎡

⎤ ⎡

⎤

⎡

⎤

=

_⎢

_{⎥ ⎢}

_{⎥ ⎢}

=

_⎥

⇒

⎢

⎥

₊

₊

⎣

⎦ ⎣

⎦ ⎣

⎦ ⎣

⎦

=

=

=

=

−

−

−

−

=

=

−

1 2 1 2 1 2 1 2 1 2 1 2 1 2

1

1

1

f f f f f f f f f f f f f f f

z

h h z y

h

h z

z g

z y

h h

h h

z y

=

=

−

₋

−

• Note the sign of i₂ and also the reverse sense of signal flow. The sign is chosen so the ABCD matrix of a cascade of two networks is just the matrix product of the individual ABCD matrices (compare this to the messy loading calculation before!) • The reverse sense of signal flow is to keep the matrix finite if an amplifier is

unilateral.

• The conversion from, say, Y to ABCD follows the same logic as the Y(H) calculation:

Transmission (or ABCD) parameters (3)

1 2 1 1 1 2 11 12 2 21 22 2 22 11 22 21 12 11 21

1

0

0

1

1

1

,

_y Y

v

A

B

v

v

A

B

v

i

C

D

i

Y

Y

v

C

D

Y

Y

v

Y

A

B

Y Y

Y Y

Y

C

D

Y

⎡ ⎤

₌

⎡

⎤

⎡

⎤

_⇒

⎡

⎤ ⎡ ⎤

₌

⎡

⎤

⎡

⎤ ⎡ ⎤

_⇒

⎢ ⎥

⎢

⎥

⎢

₋

⎥

⎢

⎥ ⎢ ⎥

⎢

⎥

⎢

₋

₋

⎥ ⎢ ⎥

⎣

⎦

⎣

⎦

⎣ ⎦

⎣

⎦

⎣

⎦ ⎣ ⎦

⎣

⎦ ⎣ ⎦

⎡

⎤

⎡

⎤ −

₌

_{Δ =}

₋

⎢

⎥

⎢

⎥

_Δ

⎣

⎦

⎣

⎦

1 2 1 2

v

A

B

v

i

C

D

i

⎡ ⎤

⎡

⎤

⎡

⎤

=

⎢ ⎥

⎢

_{⎥ −}

⎢

⎥

⎣

⎦

⎣ ⎦

⎣

⎦

Remember that all ABCD parameters are inversely proportional to the gains. This is the reason for formally choosing port 2 as the input port.

Composition rules summary

Y

₁

Y

₂

Y

₁

+Y

₂

Z

₁

Z

₂

Z

₁

+Z

₂

G

₁

+G

₂

G

₁

G

₂

H

₁

H

₂

H

₁

+H

₂

X

₁

X

₂

X

₁

X

₂

For the exact calculation of circuit interconnections we can use 2-port matrix algebra:

shunt-shunt: add Y matrices shunt-series: add G matrices

•

Calculation of the response of unilateral multi-stage amplifiers is simple:

•

Product of gains and voltage dividers.

•

Calculation of the response of non-unilateral multistage amplifiers involves

determining for each stage:

•

the effect of source impedance on gain and output impedance

•

the effect of load impedance of input impedance and gain

•

This typically leads to a set of simultaneous quadratic equations.

•

A conceptually simpler analysis method involves the transmission or “ABCD”

parameters which allow to describe all the loading effects of a non-unilateral

cascade through a matrix product.

•

With the introduction of ABCD parameters we have introduced simple ways to

describe any connection between 2-port circuits.