IJSTE - International Journal of Science Technology & Engineering | Volume 2 | Issue 10 | April 2016 ISSN (online): 2349-784X
Optimum Analysis of ALU Processor by using
UT Technique
Rahul Sharma Deepak Kumar
M. Tech Scholar Assistant Professor
Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering Vidhyapeeth Institute of Science and Technology Bhopal,
MP, India
Vidhyapeeth Institute of Science and Technology Bhopal, MP, India
Abstract
Now a day's, the main challenge in front of VLSI System designer are to design fast processing system. And the ALU are main functional unit in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. So the performance such VLSI circuit is dependent on the performance of the ALU. And the ALU speed is mainly depends on the speed of multiplier. Here, a High-speed multiplier is designed and analyzed which is based on the algorithm named as “Urdhva Tiryakbhyam” sutra (UT Technique). Traditionally, this well known Technique has been used for fast multiplication. And analyze in terms of Path delay and there by efficiency. The proposed algorithm is developed using VHDL. Implementation has been done using Xilinx14.2, Spartan 6.
Keywords: Vedic mathematics, Adder, Multiplication, Urdhva Tiryakbhyam (UT) Technique, Multiplexer
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I. INTRODUCTION
We know that the ALU is a Computation unit that performs various arithmetic (addition, subtraction, multiplication) and logical operations (AND, OR, INVERTER). And that’s why the ALU is called heart of microprocessor, microcontroller and digital signal processor. Every technology uses those operations either fully or partially which are performed by ALU. No technology can exist, without those operations which are performed by ALU. The block diagram of ALU is given below in Figure 1. The performance of Fast processing system is dependent on the speed of the ALU. And the ALU speed is mainly depends on the speed of multiplier. Here, a High-speed multiplier is designed and analyzed which is based on the algorithm named as “Urdhva Tiryakbhyam” sutra (UT Technique). Which provide following features – high speed, less power consumption, and less area or even combination of them in one multiplier. This will used in designing of various high speeds, low power, compact VLSI circuits.
Fig. 1: Block Diagram of an ALU
The organization of paper starts with a brief introduction that describes in the section I. Thereafter, Section II describes the basic methodology of Urdhva Tiryakbhyam technique. Section III describes the ripple carry adder. Section IV describes the design and implementation of proposed multiplier based on UT Technique module in XilinxISE14.2. Section V comprises of Result and Discussion in which computational path delay obtained. Finally Section VI comprises of Conclusion and future work.
II. UT TECHNIQUE
364 * 455 = 165620
Fig. 2: Multiplication of two decimal numbers: 364*455
III. RIPPLE CARRY ADDER
Optimum Analysis of ALU Processor by using UT Technique
(IJSTE/ Volume 2 / Issue 10 / 090)
For an n-bit Ripple Carry Adder Sum and Carry Equation are given bellow.
S0= A0 B0Cin (1)
C0 = A0B0+ B0Cin+ CinA0 (2)
S1= A1B1C0 (3)
C1= A1B1+ B1C0+ C0A1 (4)
S2= A2B2C1 (5)
C2= A2B2+ B2C1+ C1A2 (6)
Sn−1= An−1Bn−1Cn−2 (7)
Cn−1= An−1Bn−1+ Bn−1Cn−2+ Cn−2An−1 (8)
IV. PROPOSED MULTIPLIER ARCHITECTURE
UT Technique based Multiplier is efficient hardware architecture for multiplying two integers, compared to a normal multiplier; it is mostly used for high speed multiplication. The block diagram of 4×4 bit, 8×8 bit UT Multipliers are respectively given below in Figure 4 and Figure 5. Last two output bit P8, P9 (for 4×4 Multiplier) and P16, P17 (for 8×8 Multiplier) are Garbage Bits.
Fig. 4: Block Diagram of Proposed 4×4 UT Multiplier
V. RESULTS AND DISCUSSIONS
Fig. 5: Block Diagram of Proposed 8×8 UT Multiplier
Table – 1
Analysis of Different Bit UT Multipliers
UT Multiplier Number of slices Number of 4 input LUTs Number of Bonded IOBs Delay (ns) Used Available Used Available Used Available
2-BIT 4 2400 0 4 8 102 5.488
4-BIT 20 2400 0 4 18 102 9.332
Optimum Analysis of ALU Processor by using UT Technique
(IJSTE/ Volume 2 / Issue 10 / 090)
VI. CONCLUSION AND FUTURE WORK
In this paper we have proposed an extremely effective method of multiplication based on Urdhva- Tiryakbhyam algorithm. With this method we can construct multiplier of any number of bits, and shows the computational benefits given by UT Technique. Since our objective was to reduce the computational path delay for proposed 8x8 bit UT multiplier is found to be 16.800 ns, hence we achieved our objective.
UT multiplier designs are developed using The Ripple Carry Adder. The Ripple Carry Adder is slowest among all the adders because every full adder must wait till the previous full adder generates the carry bit for its input. If design a multiplier with efficient adder, multiplier gives better performance.
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