EE134 1
Digital Integrated Circuit (IC) Layout and Digital Integrated Circuit (IC) Layout and
Design Design
!
EE 134 – Winter 05
" Lecture Tu & Thurs. 9:40 – 11am ENGR2 142
" 2 Lab sections
– M 2:10pm – 5pm ENGR2 128 – F 11:10am – 2pm ENGR2 128
" NO LAB THIS WEEK
" FIRST LAB Friday Jan. 20
People People
!
Lecturer - Roger Lake
" Office – ENGR2 Rm. 437
" Office hours - MW 4-5pm
" [email protected]
!
TA – Faruk Yilmaz
" Office – ENGR2 Rm. 222
" Office Hours – TBD
" [email protected]
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EE134 Web
EE134 Web - - site site
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http://www.ee.ucr.edu/~rlake/EE134.html
" Class lecture notes
" Assignments and solutions
" Lab and project information
" Exams and solutions
" Other useful links
Class Organization Class Organization
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Homework assignments (10%)
!
Labs (20%)
" Tutorials to learn the Cadence design software
!
Final Project (50%)
" Design a digital circuit (eg. 4 bit adder)
" Work in teams of 3
!
Midterm (20%)
EE134
Digital Integrated Digital Integrated Circuits:
Circuits:
A Design Perspective, A Design Perspective, 2 2
ndndEd. Ed.
Jan M. Rabaey
Anantha Chandrakasan Borivoje Nikolic
Text Book Text Book
Software Software
!
Cadence software
" Online documentation and tutorials
" Sun4 UNIX Workstations
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What is this book all about?
What is this book all about?
!
Introduction to digital integrated circuits.
" CMOS devices and manufacturing technology.
" CMOS inverters and gates.
" Propagation delay,
" noise margins, and
" power dissipation.
" Sequential circuits. Arithmetic, interconnect, and memories.
!
What will you learn?
" Understanding, designing, and optimizing digital circuits with respect to different quality metrics: cost, speed, power
dissipation, and reliability
Digital Integrated Circuits Digital Integrated Circuits
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Introduction: Issues in digital design
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CMOS devices and manufacturing
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The CMOS inverter
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Combinational logic structures
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Propagation delay, noise margins, power
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Sequential logic gates; timing
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Interconnect: R, L and C
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Arithmetic building blocks
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Memories and array structures
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Design methods
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EE134 Winter 2006
EE134 Winter 2006 - - Lecture 1 Lecture 1
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Introduction
Introduction Introduction
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Why is designing digital ICs different today than it was before?
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Will it change in future?
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The First Computer (1832) The First Computer (1832)
The Babbage Difference Engine (1832)
25,000 parts cost: £17,470
ENIAC
ENIAC - - The first electronic computer (1946) The first electronic computer (1946)
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The Transistor Revolution The Transistor Revolution
First transistor Bell Labs, 1948
The First Integrated Circuits The First Integrated Circuits
Bipolar logic 1960’s
ECL 3-input Gate Motorola 1966
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Intel 4004 Micro
Intel 4004 Micro -Processor (1971) - Processor (1971)
1971
2,300 transistors 108 KHz operation
Intel Pentium 4 microprocessor (2000) Intel Pentium 4 microprocessor (2000)
42 M transistors (217 mm2)
1.5 GHz 0.18 µm
180 nm technology node
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What Happened over 30 Years?
What Happened over 30 Years?
1971 2000
2,300 transistors 108 KHz operation
42 M transistors 1.5 GHz operation
~ 15,000 x
Automotive comparison: SF to NY in 13 seconds.
Moore
Moore ’ ’ s Law s Law
#
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
#
He made a prediction that
semiconductor technology will double its
effectiveness every 18 months
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Moore
Moore ’ ’ s Law s Law
1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0
1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975
LOG2 OF THE NUMBER OF COMPONENTS PER INTEGRATED FUNCTION
Electronics, April 19, 1965.
Evolution in Complexity
Evolution in Complexity
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Transistor Counts Transistor Counts
1,000,000 100,000 10,000 1,000
10 100
1
1975 1980 1985 1990 1995 2000 2005 2010 8086
80286 i386
i486Pentium®
Pentium®Pro
K 1 Billion 1 Billion
Transistors Transistors
Source: Intel Source: Intel
Projected Projected
Pentium®II Pentium®III
Courtesy, Intel
Moore
Moore ’ ’ s law in Microprocessors s law in Microprocessors
400480088080 8085 8086
286 386
486Pentium® procP6
0.001 0.01 0.1 1 10 100 1000
1970 1980 1990 2000 2010
Year
Transistors (MT)
2X growth in 1.96 years!
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Die Size Growth Die Size Growth
40048008 8080
80858086286386 486 Pentium ® proc P6
1 10 100
1970 1980 1990 2000 2010
Year
Die size (mm) ~7% growth per year
~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s Law Die size grows by 14% to satisfy Moore’s Law
Courtesy, Intel
Frequency Frequency
P6
Pentium ® proc 486
286 386 8085 8086
8080 8008 0.1 4004
1 10 100 1000 10000
1970 1980 1990 2000 2010
Year
Frequency (Mhz)
Lead Microprocessors frequency doubles every 2 years Lead Microprocessors frequency doubles every 2 years
Doubles every 2 years
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Power Dissipation Power Dissipation
P6
Pentium ® proc 486
386 8086 286
80808085 40048008
0.1 1 10 100
1971 1974 1978 1985 1992 2000 Year
Power (Watts)
Lead Microprocessors power continues to increase Lead Microprocessors power continues to increase
Courtesy, Intel
Power will be a major problem Power will be a major problem
5KW 18KW 1.5KW 500W
40048008808080858086286
386486
Pentium® proc
0.1 1 10 100 1000 10000 100000
1971 1974 1978 1985 1992 2000 2004 2008 Year
Power (Watts)
Power delivery and dissipation will be prohibitive Power delivery and dissipation will be prohibitive
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Power density Power density
4004 8008
8080 8085
8086
286 386
486
Pentium® proc P6
1 10 100 1000 10000
1970 1980 1990 2000 2010
Year
Power Density (W/cm2)
Hot Plate Nuclear Reactor Rocket Nozzle
Power density too high to keep junctions at low temp Power densitytoo high to keep junctions at low temp
Courtesy, Intel
Not Only Microprocessors Not Only Microprocessors
Digital Cellular Market (Phones Shipped)
Analog Baseband
Digital Baseband (DSP + MCU)
Power Management Small
Signal RF Power RF
Cell Phone
(889) (836)
(776) (703)
648 513
435 162 48 Units (M)
2008 2007
2006 2005
2004 2003
2000 1998 1996 Year
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Challenges in Digital Design Challenges in Digital Design
“Microscopic Problems”
• Ultra-high speed design
• Interconnect
• Noise, Crosstalk
• Reliability, Manufacturability
• Power Dissipation
• Clock distribution.
Everything Looks a Little Different
“Macroscopic Issues”
• Time-to-Market
• Millions of Gates
• High-Level Abstractions
• Reuse & IP: Portability
• Predictability
• etc.
…and There’s a Lot of Them!
∝ (
# Transistors)∝ 1/(Transistor size)
?
Productivity Trends Productivity Trends
1 10 100 1,000 10,000 100,000 1,000,000 10,000,000
2003
1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2005 2007 2009
10 100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 Logic Tr./Chip
Tr./Staff Month.
x x x x x x
x
21%/Yr. compound Productivity growth rate
x
58%/Yr. compounded Complexity growth rate 10,000
1,000 100 10 1 0.1 0.01 0.001 Logic Transistor per Chip(M)
0.01 0.1 1 10 100 1,000 10,000 100,000
Productivity (K) Trans./Staff -Mo.
Source: Sematech
Complexity outpaces design productivity
Complexity
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Why Scaling?
Why Scaling?
!
Technology shrinks by 0.7/generation
!
With every generation can integrate 2x more functions per chip; chip cost does not
increase significantly
!
Cost of a function decreases by 2x
!
But …
" How to design chips with more and more functions?
" Design engineering population does not double every two years…
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Hence, a need for more efficient design methods
" Exploit different levels of abstraction
Design Abstraction Levels Design Abstraction Levels
n+
n+
S
G
D +
DEVICE CIRCUIT GATE MODULE SYSTEM
EE134 33
Next Class Next Class
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Introduce basic metrics for design of
integrated circuits – how to measure delay, power, etc.
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