Digital Integrated Circuit (IC) Layout and Design - Week 3, Lecture 5

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EE134 ₁

Digital Integrated Circuit (IC) Layout and

Design

-

Week 3, Lecture 5

! http://www.ee.ucr.edu/~rlake/EE134.html

Reading and

Prelab

"Week 1 - Read Chapter 1 of text. "Week 2 - Read Chapter 2 of text. "Week 3 - Read Chapter 3 of text. "Prelab - Lab 1.

! Read insert A of text, pp. 67 - 71.

! The lab will make more sense if you read this before lab.

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Agenda

"Last Lecture

! Design rules

! Layout and Design

! Ties to V_DDand GND

! Padframes

! Pin Packages

"Today’s Lecture

! Contacts

! Basic MOS transistor operation

! Large-signal MOS model for manual analysis

! The CMOS inverter

Course Emphasis / Design Styles

"Physical design of CMOS digital ICs "Application Specific IC (ASIC)

! Full Custom (What we are doing)

–Most flexible approach –Higher speed

–Smaller designs –Expensive

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Design Styles (cont.)

"ASIC (cont.)

! Standard Cell

–Logic gate level –Low volume –Quick turnaround –Lower density

! Gate Array (FPGA)

–Lowest density - speed - cost.

Flowchart

Define circuit specs Circuit Schematic

Circuit Simulation

Layout

Parasitic Extraction (R,C) Re-simulate with Parasitics

Prototype Fabrication Test and Evaluate

Meet Specs?

No

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Tie n

-

well to VDD and Substrate to

Ground

A A’ n p-substrate Field Oxide p+ n+ In Out GND VD D (a) Layout A A’ V_DD n+ V n+ p+

Reason for GND and V

_DD_DD

Ties

n p-substrate V_DD n V_out

Parasitic Diodes

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Contacts to Silicon

"Ohmic Contacts

! Metal on highly doped n+ _{or p}+ _Si.

! What you want to pin the substrate to ground or the n-well to V_DD.

"Schottky Contacts (we won’t use these)

! Metal on lightly doped n or p Si.

! Creates a Schottky diode which has an I-V curve similar to a p-n junction diode.

Ohmic

contact

"Metal on n+ or p+ Si. "Simple picture:

"Need heavy doping to get the ultra short

screening length needed for an OHMIC contact.

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Schottky

Contact

"Metal on n or p Si. "Simple picture:

"Light n or p doping gives long screening

length giving Schottky Barrier.

Ohmic

Contacts for Voltage Pinning

"Ohmic contact to the n-well

"You need the

! Active and Select to define the n+

region.

! Contact to put hole in thick passivation

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Ohmic

Contacts for Voltage Pinning

"Ohmic contact to the p-substrate

"You need the

! Active and Select to define the p+ region.

! Contact to put hole in thick passivation oxide / nitride so that the metal contacts the Si.

Pin n

-

well to V

_DD_DD

and p

-

substrate to GND

M1 V_DD M1 GND Power Bus Ground Bus PMOS NMOS p+ p+ n+ n-well n+ n+ p+

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The Active Layer

"Cut in the Field Oxide (FOX) to get down to

the Si.

Active and Select Layers

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Active and Select Layers (cont)

4 Concepts to Remember:

"Need to put down an n+ region on the n-well

to make an ohmic contact to the n-well.

"Need to put down a p+ region on the

p-substrate to make an ohmic contact to the p-substrate.

"These are your active / select layers. "Finally, you need a contact layer to drill

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BAD MOS Layout

"DO NOT DO THIS!!!!!!!

active - hole cut in FOX

n+ select

• Self-aligned process

• The Poly gate serves as an implant mask during the n+ implant.

• There is no gap between the source/gate and drain/gate. poly-gate

Outline

"MOS Transistor ! Basic Operation ! Modes of Operation

! Deep sub-micron MOS "CMOS Inverter

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What is a Transistor?

V_GS ≥ V_T R_on S _D A Switch! An MOS Transistor D S G V_GS

Switch Model of CMOS Transistor

D S G V_GS S R_on D S _D |VGS| < |VT| _|_V GS| > |VT|

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Transistor Circuit Symbols

"NMOS

Body (p-Si substrate) Drain Source Gate D S G B = S # D S G We always want D S G

Body tied to Source

B

NMOS Body Terminal (B)

M1 V_DD PMOS NMOS p+ p+ n+ n-well n+ D D Circuit Schematic Layout • A transistor is a 4 terminal device.

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Transistor Circuit Symbols

"PMOS Body (n-well) Drain Source Gate D S G B = S # We always want D S G

Body tied to Source

B V_DD

D S

G

PMOS Body Terminal (B)

D S = V_DD G B = S = V_DD M1 V_DD M1 GND PMOS NMOS p+ p+ n+ n-well n+ n+ p+ S D B Layout

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NMOS and PMOS

"PMOS is complementary to NMOS

"Turn it upside down and switch all signs of

voltages, V_SD # V_DS, V_GS # V_SG. V_GS> 0 D S G + -NMOS -V_SG> 0 D S G + PMOS

Outline

"MOS Transistor ! Basic Operation ! Modes of Operation

! Deep sub-micron MOS

"CMOS Inverter

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Threshold Voltage: Concept

The Threshold Voltage

q T k_B F = ⎟⎟ ⎠ ⎞ ⎜⎜ ⎝ ⎛ = T i A T n N ln -φ φ φ

2φ_F≈ -0.6V for p-type substrates γ is the body factor

V_T0= 0.76 V (NMOS) 0.95 V (PMOS)

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The Body Effect

V_TO reverse body bias

0 -0.5 -1.0 -1.5 -2 -2.5 V_SB 0.4 0.5 0.6 0.7 0.8 0.9 VT (V)

The Drain Current

"Charge in the channel is controlled by the

gate voltage:

"Drain current is proportional to charge x

velocity: [ GS T] ox i x C V V x V Q ( )=− − ( )− ox ox ox t C =ε W x Q x v I =− ( )⋅ ( )⋅

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The Drain Current

"Combining velocity and charge:

"Integrating along the length of the channel

from source to drain:

(V V V ) dV W C dx I_D⋅ =µ_n⋅ _ox⋅ ⋅ _GS− − _T ⋅ ( ) ∫ ∫G ⋅ =VDS _n⋅ _ox⋅ ⋅ _GS− − _T ⋅ L D dx C W V V V dV I 0 0 µ ox ox n ox n n t C k′ =µ ⋅ = µ ⋅ε ( ) _⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − ⋅ − ⋅ ⋅ ⋅ = 2 2 DS DS T GS ox n D V V V V L W C I µ n+ n+ D S G VGS x L V(x) + – VDS ID

Outline

"MOS Transistor ! Basic Operation ! Modes of Operation

! Deep sub-micron MOS

"CMOS Inverter

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Transistor in Linear Mode

n+ n+ p-substrate D S G B VGS x L V(x) + – VDS I_D VGS> VDS+ VT Device turned on (V_GS> V_T) ( ) _⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − ⋅ − ⋅ ⋅ ⋅ = 2 2 DS DS T GS ox n D V V V V L W C I µ V_DS< V_GS- V_T

Transistor in Saturation

n+ n+ S G VGS D VDS > VGS - VT V_GS - V_T + -Pinch-off V_T < V_GS < V_DS+ V_T VDS > VGS- VT ⎤ ⎡ 2 V W

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"For V_DS > V_GS - V_T, the drain current

saturates:

"Including channel-length modulation:

( )2 2 GS T ox n D V V L W C I = µ ⋅ ⋅ ⋅ −

Saturation

( GS T) ( DS) ox n D V V V L W C I =µ ⋅ ⋅ ⋅ − ⋅ 1+λ 2 2 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6x 10 -4 VDS(V) I(AD ) slope = λ V_DS = V_DS/V_A V_A= 1/λ = Early voltage

Modes of Operation

"Cutoff: "Resistive or Linear: "Saturation V_GS< V_T ID= 0 VDS< VGS- VT & V_GS> V_T V_DS> V_GS- V_T V_GS> V_T D n ₂ ox (VGS VT)2 L W C I = µ ⋅ ⋅ ⋅ − ( ) _⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − ⋅ − ⋅ ⋅ ⋅ = 2 2 DS DS T GS ox n D V V V V L W C I µ

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Current

-

Voltage Relations

A good

ol

’

Transistor

Quadratic Relationship 0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6x 10 -4 V_DS(V) ID (A ) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation V_DS= V_GS- V_T

A model for manual analysis

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Outline

"MOS Transistor ! Basic Operation ! Modes of Operation

! Deep sub-micron MOS "CMOS Inverter

Ch. 3

Current

-

Voltage Relations

The Deep

-

Submicron Era

Linear Relationship -4 V_DS(V) 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5x 10 ID (A ) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation

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Velocity Saturation

ξ (V/µm) ξ_c= 1.5 υn (m /s) υ_sat= 105

Constant mobility (slope = µ)

Constant velocity

Velocity Saturation

I_D Long-channel device Short-channel device V_GS= V_DD Saturates sooner

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I

_D_D

versus V

_GS_GS

I

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Including Velocity Saturation

µ_nchosen empirically so that sat v c n ₌ 2 ξ µ # µ_ndepends on the SPICE model.

Simple Cheesy Derivation for Velocity

Saturation and Linear Dependence on

V

_GS_GS ( ) D D TH GS ox velocity n D v W I x V V V C dx dV W I D 2 2 ) ( ρ µ ρ (chargedensity) = − − ′ = 4 4 4 4 3 4 4 4 4 2 1 3 2 1 By definition, dx dV v v n ≡_ξ = µ

(

)

sat dV v − − ′ =

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I

_D_D

versus V

_DS_DS

Regions of Operation

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A Unified Model for Manual Analysis

Simple Model versus SPICE

1 1.5 2 2.5x 10 -4 I D (A ) Velocity Saturated Linear VDS=VDSAT

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A PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0 -1 -0.8 -0.6 -0.4 -0.2 0x 10 -4 VDS(V) ID (A )

Assume all variables negative! VGS = -1.0V VGS = -1.5V VGS = -2.0V VGS = -2.5V

Sub

-

Threshold Conduction

(Cut

-

off)

0 0.5 1 1.5 2 2.5 10-12 10-10 10-8 10-6 10-4 10-2 V_GS(V) ID (A ) V_T Linear Exponential Quadratic

Typical values for S: 60 .. 100 mV/decade The Slope Factor

ox D nkT qV D C C n e I I GS + = 1 , ~ ₀ S is ∆VGSfor ID2/ID1=10 V_DS= V_DD

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Subthreshold

"Inverse sub-threshold slope (S)

! Ideal value @ T=300K, n=1,

! For each 60 mV of V_GS, the current drops by a factor of 10. This is the best that you can do.

! For V_DD= 0.4V, the maximum on-off current ratio that you can have at T=300K is

! At 373K, the ratio is ( ) decade mV 10 ln =60 = q T k S B 6 60 400 10 6 . 4 10 = × 5 74 400 10 3 . 2 10 = ×

Subthreshold

"Current in subthreshold ( DS) q T k V q T nk V S D I e e V I B DS B GS λ + ⎟⎟ ⎟ ⎠ ⎞ ⎜⎜ ⎜ ⎝ ⎛ − = / 1 − / 1 (log I ) 1 1 1 dI 1 d ⎞ ⎛ ⎞ ⎛ − −

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Subthreshold

Concepts

"FETs turn off exponentially.

( ) _{ ⎩ ⎨ ⎧ = = = mV/dec@ 100 C C 27 @ mV/dec 10 ln o_o 74 60 1 n B q T nk S

"Inverse subthreshold slope, S (mV/dec), is

the figure of merit that tells how well they shut off. 1.5 typically and ≈ ≥ 1 n

"The maximum possible on-off current ratio

is V S off on DD I I 10 |_max =

"2018 ITRS node has V_DD = 0.4V - hence the

static power problem.

Know this if you are in an interview with a semiconductor co.