Implementation of low power and fast full adder by using new XOR and XNOR gates

Author for correspondence:

Department of Electronics and Communication Engineering, Nandha Engineering College (Autonomous),

Volume-7 Issue-1

International Journal of Intellectual Advancements

and Research in Engineering Computations

Implementation of low power and fast full adder by using new XOR and

XNOR gates

R.K.Uma Maheswari

, Dr.C.N.Marimuthu

1

PG Scholar, Department of Electronics and Communication Engineering, Nandha Engineering

College (Autonomous), Erode-52, Tamil Nadu, India.

2

Professor&Dean, Department of Electronics and Communication Engineering, Nandha

Engineering College (Autonomous), Erode-52, Tamil Nadu, India.

ABSTRACT

Many existing XOR-XNOR cells suffer from non-full-swing outputs, high power consumption and low speed issues. In this paper, a new fast, full-swing and low-power XOR XNOR cell, is presented. Each of the proposed circuits has its own merits in terms of speed, power consumption, power delay product (PDP), driving ability, and so on. To investigate the performance of the proposed designs, extensive TSPICE and TANNER simulations are for XOR/XNOR and simultaneous XOR–XNOR functions are proposed. The proposed circuits are highly optimized in terms of the power consumption and delay, which are due to low output capacitance and low short-circuit power dissipation. The full swing XOR/XNOR and non-full swing XOR/XNOR gate circuits are used to propose new Full Adder design in order to optimize power, delay and PDP (Power delay product) of the low power circuits. The simulation results, based on the 65-nm CMOS process technology model,indicate that the proposed designs have superior speed and power against other FA designs performed.

Index Terms:

(XNOR).

INTRODUCTION

Nowadays, low power-consumption, high-speed circuits, and area are the design trade-offs in VLSI industries. The evolution of portable electronics, computing devices is the importance of low-power circuit design methodologies. Low-power-dissipation, least delay, and area are to need some of them important design factors for VLSI designers. To increase the performance in VLSI circuits, there is required to be less the power saving and the area. Behind these designs, driving forces have the essential Portable device different applications for less power-dissipation, minimum delay and higher throughput. Important parameters in measuring performance of VLSI systems are

speed, area, power consumption and cost. Power consumption must be reduced in a VLSI system for two main reasons. Firstly, reduction of power consumption will lead to increased density of function that can be implemented on a single IC. Secondly, in battery operated systems, it is essential to save energy for longer battery life time. These reasons play vital role in modern equipment’s due to the explosive growth in portable electronic devices like laptops, medical appliances, portable communication systems, multimedia and nonequivalent pace of improvement of battery technology and may more. Energy efficient high performance circuits are desirable for any electronics gadgets. The supporting hardware should be equally inexpensive

and compact. So, design engineers are now concentrating on efficient design of electronic components to meet critical design issues. Arithmetic operations are useful in all digital electronic systems like digital signal processing, image processing, video processing, arithmetic and logic units, floating point processor and microprocessors. Binary addition is one of the most useful operations in any arithmetic circuit. Such vast use of this arithmetic operation has created interest among the researchers to propose several kinds of new designs for the implementation of 1-bit full adder circuit in recent years An addition is an arithmetic operation, extensively used in several low-power VLSI circuits, like as specific application DSP architectures and microprocessors. These modules are used for many arithmetic operations, like as addition, subtraction [4-8]. Thus, these facts of view, the design of a full-adder circuit are having low-power-dissipations, lower the delay, and high speed performance [14, 15]. Many researchers are emphasizing on circuit performance through the minimum level of transistor count. XOR-XNOR circuit are the basic structures block of F-A. The increasing the performance of an XNOR-XOR circuit can be significantly increases the Better perform of the F-A design. Addition is one of the common and widely used fundamental arithmetic operations in many VLSI systems. Other similar arithmetic operations are subtraction, multiplication, division, address calculation etc. Using binary adders the full adder is designed and improving 1-bit full adder performance plays an important role in VLSI. Different varieties of full adders exploit completely different logic designs and technologies, which are reported in and they unremarkably aim at increasing speed and reducing power dissipation.The paper is organized as follows: in Section II, previous work is reviewed. Subsequently, in section III, the proposed design of XNOR gate, three input XNOR gate full adder are presented. In section IV, the simulation results are given and discussed. The comparison and evaluation for proposed and existing designs are carried out. Finally a conclusion will be made in the last section. The proposed method is better than previous method in providing low power circuits.

PREVOIUS WORK

Figure: 2.1 Existing Full swing of XNOR/XNOR gates

The non-full-swing XOR/XNOR circuit of Figure. 2.2 are efficient in terms of the power and delay. Furthermore, this structure has an output

voltage drop problem for only one input logical value. To solve this problem and provide an optimum structure for the XOR/XNOR gate.

Figure: 2.2 Existing Non Full swing of XNOR/XNOR gates

PROPOSED WORK

In this proposed work of this paper is to design the Low power Full adder (FA) by using full swing XOR/XNOR gates and non-full swing XOR/XNOR gates [13, 17]. In the above existing full swing XOR/XNOR gate circuit is taken to

implement full adder circuit. The proposed full adder as shown in figure 3.1. The proposed full adder by using full swing XOR/XNOR circuit has 14 transistors. Some logic manipulations can help to reduce the transistor count. The full adder was designed by using full swing XOR/XNOR circuit.

Figure: 3.1.Proposed Full adder by using full swing XOR/XNOR gates.

For instance, it is advantageous to share some logic between the sum and carry – generation sub circuits, as long as this does not slow down the

Figure: 3.2.Proposed Full adder by using non full swing XOR/XNOR gates.

The proposed full adder by using non full swing XOR/XNOR circuit has 10 transistors. The non-full-swing XOR/XNOR circuit of Figure 3.2 is having consume high amount of power and delay. Furthermore, this structure has an output voltage drop problem for only one input logical value [18- 23].Thus the SUM and CARRY is taken from the proposed circuit. The carry part of the circuit is designed 2:1 multiplexer output.

SIMULATION RESULTS

The proposed circuits are investigated in terms of power, delay and power delay product (PDP).The simulations results based on the 65-nm CMOS process technology that indicates proposed full adder circuits design.

Figure.4.1. Existing XNOR/ XOR circuit waveform

Figure.4.2.Proposed full adder by using Full swing XNOR/ XOR circuit waveform

All the net lists have been simulated using HSPICE in 65nm bulk technology. Each input is derived by two cascaded inverters. Power and delay of the inverters are included in the power

Table-1Compare the results of Full Adder (PDP in mW*µs)

S.No Architecture No. Of.

Trans

Power (mW)

Delay (µs)

PDP (nW)

1. Full swing XOR/XNOR 10 5.57 0.32 1.78

2. Non Full swing XOR/XNOR 8 1.90 7.53 14.36

3. Proposed Full adder(full swing) 14 3.87 0.73 2.82

4. Proposed Full adder(Non full swing) 10 0.43 0.2 8.73

The above table shows different Architecture and design of full swing XOR/XNOR gates and Non full swing XOR/XNOR gates [25].The Proposed Full adder design of full swing and Non full swing circuit of the Power, Delay and PDP are calculated and compared in the table.

CONCLUSION

An all including performance, analysis, and simulation have been presented in the terms of tabulated form. The Proposed full adder circuit design is derived from the different design based proposed XNOR/XNOR circuit. All the simulations outcomes using 65nm model parameter demonstrate that the simulations outcomes proposed circuitry and existing various full adders

have in points of the power-consumption, delay and PDP using TSPICE. The newly designed full adder process the merits of small delay, small Power-Delay product, saving due to lower transistor counts and special structures. In this paper, we first evaluated the XOR/XNOR and XOR–XNOR circuits. The evaluation revealed that using the NOT gates on the critical path of a circuit is a drawback. After simulating the FA cells in different conditions, the results demonstrated that the proposed circuits have a very good performance in all simulated conditions .The full swing Full adder circuit gives less amount of power and delay and also have reduce the PDP in the low power circuit for the proposed full adder compare than non-full swing full adder.

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