Chapter 3
Digital Basics
We conclude our review of basic concepts with a survey of topics from digital electronics. We confine our attention to aspects that are important in the understanding of simple devices, and in particular the analog to digital converter. As often as is practical we illustrate the concept with a LabVIEW demonstration.
Background
We have seen in Chapter 2 how a gate can be made from a manual switch, a transistor, and an operational amplifier (opamp). A gate can exist in one of only two states: ON or OFF, CLOSED or OPEN. A transistor can be conducting a current or not. An opamp’s output can be HIGH or LOW. We can think of these states of switches, transistors or opamps as representing a TRUE logic state or a FALSE logic state. The functionality of these devices, existing in only two possible states, is most naturally described by the binary number system. We begin therefore with background mathematics and basic definitions.
Number System
A number system is defined as a set of unique number elements. For example, the decimal system, the one most familiar to us (with our ten fingers and toes) has ten elements: the digits 0 through 9. Any number in the decimal system is constructed with digits from this set. The size of the set is called the base. Thus a number N in the decimal system is said to be “to the base 10” and is commonly written N10 when the base needs to be explicitly indicated.
In any system the integers making up any number have a weight depending on their position in the number. The number abcdn in the “base n” system may be written as the series:
abcd
n=
a n
3
( )
+
b n
( )
2+
c n
( )
1+
d n
( )
0 . …[3-1] The digit a has the weight n3, the digit b the weight n2, and so on. For example,1001
10=
1(1000)
+
0(100)
+
0(10)
+
1(1)
Though in principle a system may have any number of elements, the systems in most use in modern digital electronics have two, eight or sixteen elements, called the binary, octal and hexadecimal systems. We consider some aspects of each.
Binary System
The binary number system is comprised of the ele-ments 0 and 1. A number in this system is to the base 2 and is denoted N2. If a “0” is taken to stand for the one state of a digital device and a “1” for the other, then the mathematics of digital circuitry involves just 0s and 1s, or binary arithmetic.
A binary number is written as a string of 1s and 0s arranged from left to right with the digits laid out in order of decreasing significance. Each digit is called a
bit. An example is shown in Figure 3-1, the 8-bit
num-ber 110010112. Each bit is shown within a box. Shown below each box is the decimal value of each bit, and shown above each box is the decimal value expressed as a power of 2. In accordance with eq[3-1] the decimal equivalent is seen to be 20310.
1 1 0 0 1 0 1 1
ON/OFF
2n: 27 26 25 24 23 22 21 20
DEC: 128 64 32 16 8 4 2 1 The decimal equivalent is:
1x128 + 1x64 + 0x32 + 0x16 + 1x8 + 0x4 + 1x2 + 1x1 = 203.
A number may require more than bits or less than 8-bits to be completely specified. Some of the instru-ments of data acquisition you will use in this course produce floating point measurements of 8-bits, some of 10-bits, and a few of 12-bits. In comparison, state-of-the-art audio CDs have a resolution of 20 bits and current microcomputers handle data of 32 bits (with 64-bit models just around the corner). Figure 3-2 shows what a binary number can look like in terms of voltages on an RS-232 interface line.
Figure 3-2. The pulse train for the ASCII character “m”,
10910, as sent over an RS-232 interface.
Octal System
The octal number system is comprised of the eight elements: the digits 0 through 7. This system was much used in the days of mainframe computers but is little used today. We mention it here only for completeness.
Hexadecimal System
In terms of usage the hexadecimal system is next in importance to the binary system. The system is com-prised of sixteen elements: the digits 0 through 9 and the letters A through F. A, B, etc. stand for 1010, 1110,
etc. For compactness, data and computer memory locations are commonly wrtten in hexadecimal notation. In the following example problems and LabVIEW demos we demonstrate a few methods of converting from one number system to another.
Example Problem 3-1
Binary-to-Decimal Conversion Using the Method of
Positional Values
Convert the 5-bit number 101102 to N10 using the
method of positional values. Solution:
The method of positional values implements eq[3-1]: 101102 = 1(24) + 0(23) + 1(22) + 1(21) + 0(20)
= 1(16) + 0(8) + 1(4) + 1(2) + 0(1) = 16 + 4 + 2
= 22.
Thus 101102 = 2210.
If you wish you can experiment with the LabVIEW demo BintoDec.vi for the same purpose.
Running a LabVIEW Demo
To run a LabVIEW demo on a Macintosh in the physics lab do the following:
¬
Navigate from the desktop through Physics >> PSCB01S >> LabVIEW Demos >> Chapter 03 and load BintoDec.vi. LabVIEW should run.Á
When LabVIEW has finished booting it will pres-ent you with BintoDec.vi’s front panel (Figure 3-3a). To run the demo click the Run button. The demo will continue running until you click the STOP button.Â
Manipulate the vertical slide switches as you wish by clicking with the mouse in the “up” or “down” spaces. You will see the demo update the decimal value dynamically. When you wish to stop the demo, click the Stop button.Ã
With the demo stopped, but with LabVIEW still running, you might wish to examine the code of the VI. The code is contained in the Diagram window. First ensure the demo is stopped. Then select Window >> Display Diagram. The Diagram window will open (Figure 3-3b). You should be able to identify the functions Multiply and Add in the G code.Figure 3-3b. The Diagram of BintoDec.vi. This G code
im-plements the method of positional values of Example Prob-lem 3-1. The border structure is a While loop which contin-ues to execute until the stop button is pressed.
Can you recognize the method of positional values in the code?
°
At this stage, even though you may have stopped the VI, LabVIEW itself is still running. To quit LabVIEW correctly select File >> Quit. Don’t just click in the window close box.The so-called remainder method of converting from decimal to binary is illustrated in Example Problem 3-2. The demo DectoBin.vi illustrating the LabVIEW equivalent is shown in Figures 3-4a and b.
Example Problem 3-2
Decimal-to-Binary Conversion By the Remainder
Method
Convert 3910 to N2 by the remainder method.
Solution:
The remainder method of converting a decimal num-ber to binary consists of continuously dividing the number by 2 and recording the remainder. The remainders then form the binary digits. For example,
39 2 = 19 and remainder of 1 19 2 = 9 and remainder of 1 9 2 = 4 and remainder of 1 4 2 = 2 and remainder of 0 2 2 = 1 and remainder of 0 1 2 = 0 and remainder of 1 Therefore, 3910 = 1001112.
Figure 3-4a. The Panel of DectoBin.vi. The VI is shown in
its running state. Compare the switch settings with Figure 3-1.
Figure 3-4b. The Diagram of DectoBin.vi. This VI does not
employ the remainder method. The decimal number is con-verted into a boolean array whose elements are then indexed and displayed.
It is sometimes necessary to convert from decimal to hexadecimal and back again, especially when using legacy data acquisition devices. Demonstrations of decimal to hex conversion and vice versa are given in the LabVIEW demos DectoHex.vi and HextoDec.vi (Figures 3-5 and 3-6).
Figure 3-5a. The LabVIEW demo DectoHex.vi.
Figure 3-5b. The Diagram of DectoHex.vi.
Figure 3-6a. The LabVIEW demo HextoDec.vi.
Figure 3-6b. The Diagram of HextoDec.vi.
The next two example problems involve octal conver-sions. They are given here only for your information. To the knowledge of the auther, the octal system is not used in instrument remote control. In this course you will likely not have to perform octal conversions.
Example Problem 3-3
Octal-to-Decimal Conversion
Using the Method of Positional Values
Convert 24178 to N10. Solution: 24178 = 2(83) + 4(82) + 1(81) + 7(80) = 2(512) + 4(64) + 1(8) + 7(1) = 1024 + 256 + 8 + 7 = 1295. Therefore 24178 = 129510.
Example Problem 3-4
Decimal-to-Octal Conversion
Using the Remainder Method
Convert 48310 to N8. Solution: 483/8 = 60 and remainder of 3 60/8 = 7 and remainder of 4 7/8 = 0 and remainder of 7 Therefore 48310 = 7438.
BCD System
“BCD” stands for “binary-coded decimal”. The BCD system is a kind of pseudo number system in that each number in this system consists of four bits, the binary equivalent of a decimal digit. It is sometimes desireable to convert a decimal number to binary by converting each digit of the decimal number into its four-bit nibble equivalent. Thus instead of converting 9610 to its pure binary equivalent of 11000002, it is
con-verted more easily digit-by-digit, that is, first 9 and then 6 to get 1001 0110. This form of notation is called
binary-coded decimal (BCD). BCD coding is used in
LED and LCD seven-segment display devices on multimeters and other instruments (including many of those described in Appendix A). An example of the circuit is drawn in Figure 3-7a. A LabVIEW demo of this device is shown in Figure 3-7b.
Figure 3-7a. A BCD decoder used in the display of an
in-strument like a digital multimeter. Each digit is displayed by a circuit such as this one.
Figure 3-7b. The LabVIEW demo SevenSegDisp.vi
simula-ting the working of a BCD coded display.
A BCD display works in this way. Each decimal digit which is already BCD encoded is passed to a decoder. The decoder decodes the four bits by closing the cir-cuits on certain output lines. These closures result in current being passed through certain light emitting diodes (LEDs) in the display. (We have discussed the functioning of light emitting diodes in Chapter 2.) Thus for example if the BCD input were 1000 corres-ponding to decimal 8, all the lines “a” through “g” (Figure 3-7a) would be closed, resulting in all seven LEDs being lit and the digit “8” being displayed.
Boolean Algebra
All number systems, simple or complex, support an algebra. The algebra of the binary number system is called Boolean algebra, named after Boole, the 19th century French mathematician who invented it.
In Boolean algebra the letters A, B, C etc stand for logical variables which take on the values “0” (called in positive logic FALSE) or “1” (in positive logic TRUE). Three basic operations are supported:
1. Addition A + B read “A OR B”, … [3-2a] 2. Multiplication A • B read “A AND B”, … [3-2b] (also written just AB for convenience), and
3. Inversion A read “NOT A” or
“complement of A”. … [3-2c] The symbols for the operators should not be confused with the word-description of the operations. For example, the symbol for addition, “+”, represents the
operation OR (not AND); the symbol for multiplication “•” stands for the operation AND.
For example:
• The statement X = A + B means the output X is TRUE (or 1) if A or B is TRUE (or 1).
• The statement Y = A • B means the output Y is
TRUE (or 1) if both A and B are TRUE (1s).
• The statement Z = A means if A is TRUE (or 1) then Z is FALSE (0), and vice versa.
The basic operations of Boolean algebra are imple-mented with electronic devices called gates. We there-fore continue in the next section with this subject.
A Survey of Gates
Most gates in logic circuits today are integrated circuits (ICs). Gates are sold in various family types to perform various logical functions. For each gate type, there exist simple relationships between the inputs and the output that can be summarized in a special kind of table called a truth
table. The truth table lists these relationships for all possible combinations of input.
TTL Gates
There are various families of gates designed to be used at various voltage levels. We concentrate here on the most widely-used family, the TTL
(Transistor-Transistor Logic) family. In this family the voltages
corresponding to the logic states are as follows: logical 0 (LOW) 0 < V < 0.8 volts logical 1 (HIGH) 2.4 < V < 5.0 volts.
This is known as positive logic. For a gate to operate as intended these voltages must be obeyed. Any volt-age between 0 and 0.8 volts corresponds to a logic 0, any voltage between 2.4 and 5.0 volts corresponds to a logic 1. Thus the TTL family is fairly forgiving in terms of voltage. However, a voltage between 0.8 volts and 2.4 volts represents an undefined state and therefore an undefined logic. An undefined state should be avoided since a gate that is operated in this voltage range will produce an unpredictable output.
There are seven fundamental TTL logic gates: the AND, OR, NOT, NAND, NOR, exclusive-OR (XOR), and exclusive-NOR (XNOR) gates. We consider each one in turn.
AND Gate
The AND gate (Figure 3-8a) has two or more inputs (A, B, etc.) and performs the operation “•”. Its output X is 1 only if all inputs are 1; otherwise its output is 0. The truth table is shown in the figure. The table should be read row by row. For example, the second row shows that when A is 0 and B is 1, X is 0, and so on.
A B X = A • B X A 0 0 1 1 B 0 1 0 1 X 0 0 0 1
Figure 3-8a.Circuit symbol, algebraic representation, and truth table for a two-input AND gate.
The Panel of the LabVIEW demo AND gate.vi is shown in Figure 3-8b.1 See if you can reproduce the truth table by manipulating the buttons. In principle, an AND gate can have any number of inputs; Figure 3-9 shows the Panel of a 3-input AND gate demo.
Figure 3-9. The LabVIEW demo 3AND gate.vi.
OR Gate
The OR gate (Figure 3-10) performs the operation “+”. Its output is 1 when any input is 1, and 0 only if all inputs are 0. The Panel of the LabVIEW demo Or
gate.vi is shown in Figure 3-10b.
A B X = A + B X A 0 0 1 1 B 0 1 0 1 X 0 1 1 1
Figure 3-10a. Circuit symbol, algebraic representation, and
truth table for a two-input OR gate.
Figure 3-10b.The LabVIEW demo OR gate.vi.
NOT Gate
The NOT gate (Figure 3-11) performs inversion. (The insertion of an open circle in a line of a logical circuit conventionally denotes inversion.) The single output is the complement of the single input; i.e., the output is 1 if the input is 0, and the output is 0 if the input is 1. A X X = A A 0 1 X 1 0
Figure 3-11. Circuit symbol, algebraic representation, and
truth table for a NOT gate (inverter).
NAND Gate
The NAND gate (Figure 3-12) performs two operations one after the other: an AND followed by a NOT. The symbol consists of a normal AND gate symbol with an open circle at the output. The Panel of the LabVIEW demo is shown in Figure 3-12b.
A B X X = A • B A 0 0 1 1 B 0 1 0 1 X 1 1 1 0 Figure 3-12a. A input NAND gate consists of a
two-input AND gate plus inversion.
NOR Gate
The NOR gate (Figure 3-13) performs an OR followed by a NOT. The Panel of the LabVIEW demo NOR gate.vi is shown in Figure 3-13b. A B X X = A + B A 0 0 1 1 B 0 1 0 1 X 1 0 0 0 Figure 3-13a. A two-input NOR gate.
Figure 3-13b. The LabVIEW demo NOR gate.vi.
The next two gates, though available as single ICs and represented by single circuit symbols, are derivative in the sense that they consist of combinations of AND, OR, and NOT.
Exclusive-OR Gate
The exclusive-OR (XOR) gate (Figure 3-14) performs an operation denoted by the symbol ⊕. The gate has two inputs and an output which is 1 when the inputs are different (1 and 0, or 0 and 1), and an output 0 when the inputs are alike (1 and 1, or 0 and 0).
A B X A 0 0 1 1 B 0 1 0 1 X 0 1 1 0 X = A ⊕ B
Figure 3-14b.The LabVIEW demo XOR gate.vi.
Exclusive-NOR or Equality Gate
The exclusive-NOR (XNOR) gate (Figure 3-15a) performs the ⊕ operation followed by a NOT. The output is 1 when the inputs are equal and 0 otherwise. The gate is therefore also called an equality gate. The Panel of the LabVIEW demo XNOR gate.vi is shown in Figure 3-15b. A B X A 0 0 1 1 B 0 1 0 1 X 1 0 0 1 X = A ⊕ B
Figure 3-15a. An exclusive-NOR or equality gate.
Figure 3-15b. The LabVIEW demo XNOR gate.vi.
near-transistors. It is instructive to decipher the transistor equivalent of simple gates. Here is one example.
Example Problem 3-5
Gate Identification
With reference to the operation of the transistors explain that the following circuit functions as an OR gate. Confirm this result by means of a truth table. (The values of the resistors are not important to your answer.) + 6V 10 kΩ 10 kΩ 4.7 kΩ A B Z Solution:
If the voltages applied to both A and B are HIGH (1) then both transistors are saturated, the current flow through them is at a maximum and the voltage drop across the 4.7 kΩ resistor is in a HIGH (1) state. Thus two input HIGHs give an output HIGH and we have the first row in the truth table below. If the voltages applied to both A and B are LOW (0) then both transistors are cut off, neither transistor conducts and the voltage across the 4.7 kΩ resistor is in a LOW (0) state. If any one of A or B is HIGH (1), then the output is also HIGH (1) by similar arguments. The truth table is as follows. A B Z 1 1 1 0 1 1 1 0 1 0 0 0
This truth tables describes the functioning of an OR gate.
Gate Synthesis
In digital electronics the NAND gate is considered to be the basic building block from which all other gate operations can be constructed. Today, the gates we have described in the previous section are readily available as ICs, and from a number of manufactur-ers. In principle, there is no need to derive a gate operation from other gates.
In practice, however, it is often expedient to syn-thesize gate operations, especially when constrained to do so by your circuit design. For example, when using a chip that contains many gates, you may wind up with extra unused gates, and may wish to use them up by synthesizing an operation rather than using a dedicated, single gate.
We shall see in this section that the NOT gate can be formed from a NAND gate with inputs joined; an AND gate can be formed from a NAND gate followed by a NOT. Other gates can be derived following the rules of Boolean algebra.
De Morgan’s Theorems
De Morgan’s theorems are important in implement-ing gate combinations; they allow one to switch bet-ween AND (or NAND) and OR (or NOR) gate implemen-tations. De Morgan’s theorems may be written:
1.
A + B + C ...= ABC...
…[3-5a] 2.A
•
B
•
C...
=
A + B+ C...
…[3-5b] These theorems are useful in gate synthesis as we shall show in the next section.OR Gate Synthesized from NAND Gates
If the NAND gate is taken as the natural building block then an OR gate may be synthesized from 3 NAND gates by connecting them together as shown in Figure 3-16. The segmented truth table for this circuit is given in Table 3-1. You can see that the last column of this table is identical to the truth table for A + B. You can prove this with the help of de Morgan’s theorem (Figure 3-16). This is only one example of gate synthesis.
A B A B A • B = A + B = A + B
Figure 3-16. This circuit illustrates how to synthesize an OR
gate from three NAND gates with the help of de Morgan’s theorem.
Table 3-1. Segmented truth table for the synthesized OR gate of Figure 3-16. 0 0 1 1 0 1 0 1 1 1 0 0 1 0 1 0 1 0 0 0 0 1 1 1 A B A B A • B A • B
Binary Arithmetic
Like any arithmetic, binary arithmetic must include the standard operations of addition, subtraction, multiplication, and division. Here we look briefly at binary addition. The physical process of addition, say how it is done with pencil and paper, can be sum-marize with a truth table and then mechanize with logic gates.
Binary Addition
As we have seen, the binary system includes only two elements. Addition is therefore simple. Some exam-ples are shown in Figure 3-17. Numbers in binary can be added in columns much like numbers in decimal. Note that 1 plus 1 yields a sum of 0 and a carry of 1 into the next column to the left, producing an answer of 102. Similarly, 1 plus 1 plus 1 yields a sum of 1 and
a carry of 1 into the next column to the left. Binary numbers, like decimal numbers, can be added column by column working from right to left.
0 0 0 0 1 1 1 1 10 1 1 1 11 + + + +
The Half Adder
We can now investigate the mechanization of binary addition. For this purpose we consider only 2-bit numbers using the following notation: X1X0 and Y1Y0,
where the subscript refers to the order of the bit. Of course, X0, X1 etc. can take only the values 0 or 1.
Starting with the 0th bit, we can write
X
0+
Y
0=
C
1Z
0, …[3-6] where C1 is the carry from the addition of the two 0thorder bits over into the 1st order bit position. The addition of the two 2-bit numbers can therefore be represented in this way:
Carry bits C2 C1
2-bit number X1 X0
2-bit number Y1 Y0
Z2 Z1 Z0
The result Z2Z1Z0 is, in general, a 3-bit number. The
truth table for the operation given in eq[3-6] is given in Table 3-2. This operation is called half addition because no provision exists for dealing with an initial carry (or carry in).
Table 3-2. Truth table for a half-addition.
0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 X0 Y0 C1 Z0
This table is represented by the following Boolean statements:
C
1=
X
0•
Y
0, …[3-7a]and
Z
0=
X
0⊕
Y
0. …[3-7b]The second of these equations describes the Sum oper-ation, the first describes the Carry. These equations can be “mechanized”, that is, they can be represented by real, physical gates. With a little reflection you can see that the Carry operation is given by an AND gate
dashed rectangle) is called a half adder. The LabVIEW demo HalfAdder.vi that illustrates this is shown in Figures 3-18b and c. A B Sum Carry S = A ⊕ B C = A • B Figure 3-18a. Mechanization of a half-adder using an AND
gate and an exclusive-OR gate.
Figure 3-18b. The panel of the LabVIEW demo HalfAdder.vi.
Figure 3-18c. The diagram of the LabVIEW demo
Half-Adder.vi. Note how the G code resembles the circuit diagram of Figure 3-18a.
The half adder can only add two 1-bit numbers. It cannot be used to add two 2-bit numbers because in general the result is a 3-bit number. The sum of the 21
column involves three bits: one bit from each of the two numbers being added and a carry-in bit from the units column. Thus a full adder for two 2-bit numbers must be able to process three input variables. The full adder we consider next.
The Full Adder
The process of full addition must allow for an initial, or carry-in bit and a final, or carry-out bit. General-izing Table 3-2 with a carry-in bit (C1) gives the truth
table shown in Table 3-3. C2 is the carry-out bit.
There are two results of a full addition: the result Z1
and the carry bit C2. Let us consider them separately
as we did for the half adder. From Table 3-3 you can see that
C
2=
X
1•
Y
1+
C
1•
Y
1+
C
1•
X
1. …[3-8] This expression can be mechanized using three AND gates and a three-input OR gate (Figure 3-19).Table 3-3. Truth Table for a Full Adder.
0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 C1 X1 Y1 C2 Z1
You should be able to show also from Table 3-3 that
Z
1=
C
1⊕
(
X
1⊕
Y
1)
. …[3-9]Mechanizing this expression in conjunction with the majority detector of Figure 3-19 drawn as a black box gives the full adder circuit shown in Figure 3-20. A full adder is commonly represented as a rectangle with three inputs and two outputs. The LabVIEW demo FullAdder.vi is shown in Figures 3-20b and c.
This is the simplest kind of binary adder. It is also the slowest as each column of the sum must wait on the resulting carry bit from its adjoining lower-order column. This is known as serial carry propagation. Modern packages are described as 4-bit sum plus carry. These 4-bit sum plus carrys may be serially propagated to create an 8-bit sum plus carry, the smallest truly useable circuit in 8-bit devices.
C2 = X1 • Y1 + C1 • Y1 + C1 • X1 C1 X1 Y1 C1•X1 C1•Y1 X1•Y1 C2
Figure 3-19. Mechanization of the carry bit from a full
addition. This is called a majority detector.
C2 Z1 X1⊕ Y1 C1 Y1 X1 Majority detector Sum Carry
Figure 3-20a. Mechanization of a full adder.
Figure 3-20b. The LabVIEW demo Full adder.vi.
Figure 3-20c. Diagram of the LabVIEW demo Full adder.vi.
This concludes our survey of a few of the basics of digital electronics. We spend the rest of our time in this chapter on the subject of analogue-to-digital conversion.
Analog to Digital Conversion
At the heart of a digital instrument is an analog-to-digital converter (ADC). There are three common types or techniques of analog converter: parallel (also called flash conversion), successive
approximation and dual slope integration.
Terminology
Each type of ADC has its own conversion time , absolute
accuracy and resolution. Resolution is the number of
bits to which the analog signal is converted. Absolute accuracy is expressed in bits. The absolute accuracy, in bits, times the voltage value represented by the least significant bit gives the absolute accuracy in volts. Conversion time is the time it takes the converter to take an analog signal and convert it to its binary equivalent.
Parallel Conversion
A parallel (flash or simultaneous) converter employs a series of comparator circuits as is shown in Figure 3-21. (For a description of a comparator see the discus-sion of the opamp in Chapter 2.) This particular exam-ple is a 3-bit parallel ADC that uses seven compara-tors. Parallel converters require 2n – 1 comparators where n is the resolution in bits. Thus a 12-bit parallel converter would require 4,095 comparators!
The chain of resistors in the figure provides a reference or trip point voltage for each comparator. The trip point of each successive comparator is equal-ly spaced in voltage, say ∆V. Each value of ∆V
repres-ents one bit. The voltage to be converted Vin is applied simultaneously to the other input of each comparator. Comparator A trips at the lowest input voltage, comparator G at the highest.
To give the simplest example, if Vref = 7.0 V then ∆V = 1V; the trip point for comparator A is 0.5 V, B is 1.5 V, C is 2.5 V, D is 3.5 V, E is 4.5 V, F is 5.5 V and G is 6.5 V. Thus if Vin were 4.9 V, comparators A through E would trip, while F and G would remain unchanged. The decoder circuitry would convert the 0011111 (high to low) on its input lines to the 3-bit value 101, representing a voltage in the range of 4.50 to 5.49 V (the decoding is summar-ized in Table 3-4).
Thus the parallel or flash nature of the ADC should be apparent. This is the fastest of the three ADC types and is widely used in the audio industry. Though a 3-bit ADC as considered here is of little use, 20-3-bit converters are now widely available, with conversion frequencies in the 100 MHz range.
1/2 R R R R R R R 1/2 R A B C D E F G Decoder Circuitry Vref Vin MSB NMSB LSB 6.5 5.5 4.5 3.5 2.5 1.5 0.5 0 0 1 1 1 1 1 1 0 1
Figure 3-21. A parallel or flash 3-bit ADC.
Table 3-4. Data for the 3-bit flash converter.
Vin Range (Volts) Comparator A B C D E F G Encoded Binary MSB LSB 0-0.49 0 0 0 0 0 0 0 0 0 0 0.5-1.49 1 0 0 0 0 0 0 0 0 1 1.5-2.49 1 1 0 0 0 0 0 0 1 0 2.5-3.49 1 1 1 0 0 0 0 0 1 1 3.5-4.49 1 1 1 1 0 0 0 1 0 0 4.5-5.49 1 1 1 1 1 0 0 1 0 1 5.5-6.49 1 1 1 1 1 1 0 1 1 0 > 6.5 1 1 1 1 1 1 1 1 1 1
Successive Approximation
The successive approximation converter is one of the least expensive and therefore most popular ADC types. Substantially faster than a ramp ADC, it has a constant and known conversion time. This circuit (Figure 3-22) employs a digital-to-analogue converter (DAC—roughly the opposite of an ADC) and a com-parator to compare the voltage to be measured with the output of the DAC. The input to the DAC is provided by a successive approximation circuitry triggered by the output of the comparator.
Successive Approximation Circuitry Digital Outputs DAC Clock Analogue Input Comparator SAR
Figure 3-22. Block diagram of a successive-approximation
ADC.
A conversion can be described in terms of the following algorithm:
1 Zero the DAC and reset its digital input (the successive approximation register or SAR). 2 Set the MSB of the SAR, thereby producing an
output VDAC.
If VDAC is greater than Vin, then turn that bit off else if VDAC is less than Vin, leave the bit on.
3 Repeat step 2 for the next MSB, until all n bits of the SAR have been set and tested.
4 After n cycles, the digital output of the SAR will contain the digitized value of the input signal. The algorithm can be followed by studying the work-ing of the LabVIEW demo SAR.vi (Figure 3-23a). The graph on the panel shows the input waveform (dashed line) and the output of the SAR over about 8 clock cycles. The input waveform is, by default, the constant value 153 (which can be changed). The
15310 = 100110012.
The SAR algorithm states that the MSB, having the value of 128, is to be tested first. Because 128 is less than 153, the MSB is to be kept. The best estimate after the first cycle is 1000 0000. On the next cycle, the next MSB, having value 64, is added to the best estimate (that is, 128 + 64 = 192). Because 192 is greater than 153, this bit is not kept, and the best estimate remains 1000 0000. In the following cycle, the next bit value of 32 yields a test value of 128 + 32 = 160. Again, the test value is greater than the input level, so this bit is not kept, and the best estimate remains at 1000 0000. In the following cycle, the next test value of 16 yields 128 + 16 = 144. This value is less than 153, so this bit is kept. After 4 cycles, the best estimate is 1001 0000. The remaining cycles can be seen on the panel of SAR.vi.
Figure 3-23a. The panel of SAR.vi showing on the graph a
typical DAC output of successive-approximation ADC converter as a function of clock cycle.
To get the most out of the demo do the following:
¬
Load and run SAR.vi in continuous mode.Á
Use the Operate Value tool to change the input level, and observe the SAR output waveform. Change the level over a wide range, greater and less than 128. Is the input level always digitized in the same 8 clock cycles?“Abort” button.
Figure 3-23b. The Diagram of SAR.vi.
Though slower than the flash converter, successive approximation converters are relatively fast, in the range of µs. Typical conversion times at the time of writing are 1 µs for a 10-bit ADC and 2 µs for a 12-bit ADC. We shall see in Appendix A that this method is used in a number of data acquisition (DAQ) cards produced by National Instruments, in particular the PCI-1200 card installed in many of the computers in the physics lab.
Example Problem 3-6
Conversion Time
A 12-bit PCI-1200 DAQ card with a successive approximation ADC is installed in a computer whose clock frequency is 233 MHz. In principle, what should be the approximate conversion time? Comment on the result.
Solution:
According to the method of successive approxima-tions, a 12-bit conversion takes 12 clock cycles. Thus in principle the conversion time should be
12
cycles
conversion
x
233x10
1
6seconds
cycle
=
51.5ns
This number is an absolute minimum conversion time. The actual time will depend on factors such as the bus width. If the ADC is 12 bits but the bus width
is only 8 bits as in the case of the PCI-1200 the effec-tive conversion time is increased.
Integrating Type: Dual Slope Conversion
The dual slope integrating ADC works via the charge and discharge of a capacitor (Figure 3-24). The capacitor is charged from zero volts by a current proportional to the input voltage for a given time. Then the input voltage is disconnected and the capac-itor is discharged back to zero volts by a constant cur-rent source whose value is known. Figure 3-24 shows the capacitor voltage as it goes through the charge/ discharge cycle. Since the discharge time is propor-tional to the value of the constant current and the voltage on the capacitor, a digital representation of the discharge time (in clock cycles) is the digital value of the input voltage.
Voltage on Capacitor Current proportional to input voltage charges capacitor for a fixed number of clock cycles large input voltage small input voltage Time zero
detect zerodetect
Figure 3-24. Charge and discharge cycle for integrating
ADC.
This kind of ADC is commonly found in inexpensive hand-held DMMs, such as the Radio Shack Manual/Auto Range DMM (discussed in Appendix A and Lab #1).
A Working Circuit
A working ADC is shown in block form in Figure 3-25. It consists essentially of two functional blocks, a signal conditioner and the ADC chip itself. The signal conditioner is a variable-gain amplifier that allows for calibration for a variety of sensors. The ADC in this particular case is the ADC0804, an 8-bit converter.
Gain DC Offset A/D Converter DC Input 8 Digital IO Lines Write Data Pwr
Figure 3-25. Block diagram of the ADC0804 analogue to
digital converter.
The ADC0804 responds to a change in an AC voltage very quickly, in fact at a rate greater than 1000 per second. The ADC0804 converts each sample to digital form and places the signal on 8 digital input/output
(IO) lines which can then be read by a computer. The ADC0804 accepts an analogue input of 0-5 volts DC and converts it to a binary number between 0 and 256. With a maximum range of 5 volts and 256 steps between 0 and 5, resolution is 5/256 = 0.0195 volts, or almost 20 mV. So for any analogue input voltage bet-ween 0.0000 and 0.0195, the ADC0804 will produce a binary 0 (00000000); for any voltage between 0.0195 and 0.0390, a binary 1 (00000001), and so on.
The signal conditioner is present to enable one to process analogue signals smaller than 5V. For exam-ple, without the signal conditioner a signal as small as 40mV maximum would only give rise to two binary values. Such a signal would therefore be amplified to a value close to the maximum range of the IC and therefore result in much finer increments. The output would then be scaled back to the appropriate value by the computer software that is used to monitor the IO lines.
What Was Left Out
This brings us to the end of our review of digital basics.
Practice Problems
1. Convert the following numbers to decimal: 1012,110012, 1011012.
2. Convert the following numbers to binary: 10010,
22510, 12910.
3. Convert the following numbers to decimal: 100078, 12348, 5518, 628, 7778.
4. Convert the following numbers to octal: 2710,
262610, 90510, 20610, 409510.
5. Convert the following numbers to BCD: 12710,
120010, 1357642810.
6. Write a G program to perform octal-to-decimal conversion.
7. Write a G program to perform decimal-to-octal conversion.
8. Apply Boolean theorems to reduce the following expressions to simplest form:
1 + 1 + 0; 1 • 1 • A; M • M • 1; X • 0 + 1; C • 1 + D D; A + 0 + A + 0; A + B + 1;
1 (E + E); H + H + H + H; 1 • 0 • A.
9. Remove common factors to simplify the following expressions:
A + A + B; AB + CDD + BD + 1; A (A + B) + C. 10. Prove these expressions by means of truth tables:
A(A+B) = A; A+BC = (A+B)(A+C).
11. Draw a block diagram corresponding to each of the following equations. Label all terminals. Assume that the variables are available in non-inverted form only, i.e., if an non-inverted form of the variable is required, a NOT circuit must be used. X = AB; Y = ABC + AB C; Z = A + B + C;
X = A + B; Z = AB + AB.
12. Complete the following truth table for the expres-sions shown: 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 A B+C A B C A B C ABC A+B+C
13. Perform the following binary additions:
1010 1010101 11011
+ 0101 +1010101 +00111
14. The three-input OR gate follows the Boolean state-ment Q = A + B + C.
(a) Make a truth table for this gate.
(b) Write the Boolean statement for Q and mech-anize the result using 2-input NAND gates and inverters.
15. An experimenter observes that the output of a TTL NAND gate is 0 V with both inputs open and does not change when they are both connected to +5 V. Is the gate malfunctioning? Why or why not?
16. It is required that Q be true only when the logic signal A equals the logic signal B. Make a truth table of this problem, mechanize the result directly assuming that only A and B signals are available (not A or B), and then use de Morgan’s theorem to reduce this to a three-gate
mechaniza-tion from A and B inputs.
17. With detailed reference to the operation of the transistors (and by means of a truth table) confirm that the following circuit functions as a NOR gate. (The values of the resistors are not important to your answer.
+ 6V 10 kΩ 10 kΩ 4.7 kΩ A B Z
18. With detailed reference to the operation of the transistors (and by means of a truth table) confirm that the following circuit functions as a AND gate. (The values of the resistors are not important to your answer.
+ 6V 4.7 kΩ 10 kΩ A 10 kΩ B Z
19. With reference to problem 17 construct a NAND gate. Justify the operation of your gate by means of description and a truth table. (The values of the resistors are not important to your answer.
20. Write a program in G to prove the synthesized circuit of Figure 3-12.
EndNotes for Chapter 3
1 These demos were modified by the author from ones written by B. Paton in Fundamentals of Digital Electronics (National
Instruments, 1998). I am especially indebted to Prof. Paton for SAR.vi in his Lab #9 and its use in illustrating the successive approximation ADC.
