Digital Logic Design Sequential circuits

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Digital Logic Design

Sequential circuits

Dr. Eng. Ahmed H. Madian

E-mail: [email protected]

Dr. Eng. Rania.Swief

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Dr. Eng. Ahmed H. Madian 2

Registers



An nbit register consists of a group n flip

-flops capable of storing n bits of binary info.



All Flip-flops are connected to one

clock

source



Each flip-flop can store one bit of Info.



Clear signal during normal operation is set

to high

The clear input is useful for clearing all the

content of the register to all 0’s

Problem:

Typically don’t want to load

every clock



Solution:

use a external signal to

control the operation of the load

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Registers with Parallel Load

1

0

1

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Shift Registers

 A register capable of shifting its binary information in one or both direction is called a shift register

 A chain of flip-flops connected in cascade

010

SI CLK Qa Qb etc

0 Qa

Qb

Qc

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Universal Shift Registers

S1 S2 Action 0 0 No Change 0 1 Shift Right 1 0 Shift Left 1 1 Parallel Load  No Change  Shift Right  Shift Left  Parallel Load

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Basic Sequential Circuits

• Ripple Counters.

• Synchronous Counters.

• Counters with Unused States.

• Up/Down Counters

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010 100 110 011 001 000 101 111 3-bit up-counter

current state next state 0 000 001 1 1 001 010 2 2 010 011 3 3 011 100 4 4 100 101 5 5 101 110 6 6 110 111 7 7 111 000 0

Counters

 A counter is a register that goes through a predetermined sequence of stat es upon the application of clock pulses.

 Counters are a specific type of sequential circuit.

 Like registers, the state, or the flip-flop values themselves, serves as the “output.”

 The output value increases by one on each clock cycle.

 After the largest value, the output “wraps around” back to 0.  Counters could be implemented with flip-flops (JK-, D-, T-FFs)

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JK (or T) Flip flop

•A JK( or T) flip flop toggles when both inputs are 1. In this

case it effectively counts every second clock pulse:

Sometimes called a “scale of 2 counter”

1 J K clock Q ~Q clock Q

You can also say it counts from 0 to 1 and back again.

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Counter

• Connect two such flip flops together:

1 clock Q1 ₁ Q2 clock Q1 Q2 Q2Q1: 00 01 10 11 00 Complete the

timing diagram for Q2

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Counter (From D-FF)

D Flip-Flop

Frequency Divider

CLK

_A

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4-bit Ripple counter (Asynchronous)

e.g. A 4 bit ripple counter using negative edge triggered T and D FFs

Asynchronous means each flip flop is triggered by the preceding one.

Negative edge

Trigger A1 to toggle

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Dr. Eng. Ahmed H. Madian

Counters

• Synchronous counters

– Outputs of all the

flip-flops change at the

same time

– e.g. a 2-bit synchronous

counter

J K Q Q 1 1 J K Q Q clk Q_a Qb C 0 1 Q_a 0 1 0 1 00 01 10 11 00 01 Q_b

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Synchronous counter

using (JK-FF)

All flip-flops driven with the same

clock

If count enable =1 the count

begins

The flip-flop of the least significant

position (ex. A

₀

) is complemented

with every pulse

Other flip-flops is complemented

when all the bits in the lower

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10/27/20

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Unused states

• The examples shown so far have all had 2n states, and used n flip-flops. But sometimes you may have unused, leftover states

• For example, here is a state table and diagram for a counter that repeatedly counts from 0 (000) to 5 (101).

• What should we put in the table for the two unused states?

Present State Next State Q2 Q1 Q0 Q2 Q1 Q0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 ? ? ? 1 1 1 ? ? ?

001

010

011

100

101

000

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Unused states can be don’t cares…

• To get the simplest possible circuit, you can fill in don’t cares for the next states. This will also result in don’t cares for the flip-flop inputs, which can simplify the hardware.

• If the circuit somehow ends up in one of the unused states (110 or 111), its behavior will depend on exactly what the don’t cares were filled in with.

Present State Next State Q2 Q1 Q0 Q2 Q1 Q0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 x x x 1 1 1 x x x

001

010

011

100

101

000

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…or maybe you do care

• To get the safest possible circuit, you can explicitly fill in next states for the unused states 110 and 111.

• This guarantees that even if the circuit somehow enters an unused state, it will eventually end up in a valid state.

• This is called a self-starting counter.

Present State Next State Q2 Q1 Q0 Q2 Q1 Q0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0

001

010

011

100

101

000

111

110

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Example

• Design a 3-bit counter synchronous that

could count up or down directions using

one control signal “Down”

– If Down = 1 it counts down from (111 to 000)

– If Down = 0 it counts up from (000 to 111)

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Up-Down Counter state diagram

010 100 110 011 001 000 101 111 3-bit up-down counter

Down = 1

000-> 111 -> 110 -> 101 -> …..

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Up-Down Counter (From D-FF)

Present State Next State

Q2(t) Q1(t) Q0(t) Q2(t+1) Q1(t+1) Q0(t+1) 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0