low-power/high-speed applications
Adiabatic Logic Circuits for Low Power, High Speed Applications
... As technology is shrinking down we requires devices which consume less power gives less delay in device. So here we compare PFAL (Positive Feedback Adiabatic Logic) and ECRl (Efficient Charge – Recovery Logic) ...
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Design and Simulation of a Novel 8T SRAM Cell for Low Power High Speed Applications
... Proposed SRAM cell gives very less power dissipation and high noise margin which is used in the memory design purpose. By selecting sense amplifier row decoder, recharge circuit SRAM memory can be design. ...
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Design and Implementation of Compact Booth Multiplier for Low power, Low Area & High Speed Applications
... The multiplier design is mostly classified into two types which is signed and unsigned multiplier. In the signed multiplier it will perform both positive and negative multiplication. But in the unsigned multiplier is ...
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Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications
... present applications demands high speed, low power dissipation, minimum area, low noise and application specific ...wide applications. On the down side the flash ADC ...
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Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications
... to high energy ...a high energy radiation particle ...a high energy radiation particle strike flows through a p-n junction, from n-type to p-type diffusion ...
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A Gate Diffused Input Based CMOS Full Adder Circuit for Low Power, High Speed Applications
... reduce power dissipation, energy consumption and ...many applications in ...reduce power and delay in the CMOS adder ...with power gating adder circuit. In power gating method, sleep ...
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High Speed and Low Power Dynamic Latched Comparator for PTL Circuit Applications
... systems. Speed and resolution are two important factors which are required for high speed ...on-chip high-speed dynamic latched comparator for high frequency signal ...higher ...
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Efficient Implementation of 32 Bit PASTA for Low Area, High Speed and Low Power Applications
... The Parallel Self Timed Adder (PASTA) design is systematic and easy. Half adder and multiplexers are used for PASTA design. The architectural design and CMOS implementation are explained. The disadvantage of PASTA is, it ...
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Low Power And High Speed Efficient Multiplier Design
... Parallel multipliers are essential building hinders in mixed media and advanced numerous applications, the sources of info and the yield of the multiplier have a similar piece width. These circuits are indicated ...
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1. Design of low power and high speed multiplier
... DSP applications where a multiplier plays a crucial role consist of digital filtering, digital communications and several ...therefore high-speed multiplier is much desired ...computing power ...
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Low Voltage High Speed 8T SRAM Cell for Ultra Low Power Applications
... the power dissipation is also very ...is high delay due to which the performance of read and write operations are severely ...the power consumption is high. For low power ...
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Analysis of Low Power, Area and High Speed Multipliers for DSP Applications
... In DSP applications, the speeds of the multipliers are very important. This multiplier works well for signed bit multiplication. The process is same for both negative and positive numbers. In multiplication three ...
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Dual Edge Adaptive Pulse Triggered Flip-Flop for a High Speed and Low Power Applications
... between high-speed and sub threshold circuits, such as having serious timing un certainty and high sensitivity to process ...the speed of sub threshold operations. High-performance ...
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Review on Design Approach for FPGA Implementation of 16-Bit Vedic Multiplier
... a high speed and low power 16x16 Vedic Multiplier is designed by using low power and high speed modified carry select ...introduces high delay block and also ...
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High-Speed and Low-Power Flash ADCs Encoder
... include high delay because of using series logic gates; therefore at high- speed applications they should be used flip-flips or latches in between of these ...complexity, power ...
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An Improved Low Power, High Speed CMOS Adder Design for Multiplier
... general speed execution in current computerized incorporated circuits, their speed improvement is essential in elite applications, and common place application by and large requires adjustment ...
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Low Power High Speed Differential Current Comparator
... bandwidth, high speed, better noise figure and smaller supply ...its applications in circuits like current steering DACs where fast computation is necessary, neuromorphic electronic system [5] where ...
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VLSI Implementation of an Approximate Multiplier using Ancient Vedic Mathematics Concept
... Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). It mainly deals with Vedic mathematical ...
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1 5mW,14 68V/µS Low Power and High Speed Comparator Design for ADC Applications
... comparator for 0.5 V supply voltage in 0.12 μm CMOS,” IEEE Electron.Lett., vol. 43, no. 7, pp. 388–390, Mar. 2007 16. D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage ...
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A Survey on Area Efficient Low Power High Speed Multipliers
... of high-speed, area efficient and low-power VLSI architecture needs efficient arithmetic processing ...other applications multiplier is an important basic building ...of high ...
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