ultra low power

invasive monitoring of patients. However, there are two main challenges faced by the IoT-enabled medical devices: energy- efficiency and security/privacy concerns. An ultra-low power and secure IoT sensing/pre- processing the prediction of ventricular arrhythmia using ECG signals. the proposed architecture is designed using an Application Specific Integrated Circuits design flow in 65-nm Low Power Enhanced technology. it consumes the power of 62.2% less than that of the state-of-the-art approaches, it occupying 16.0% smaller area. The proposed system uses ECG key that enables protection of communication channel and offers protection also at the hardware level that means protect from reverse engineering. The security infrastructure is kept at 9.5% for area and 0.7% for power.

ABSTRACT: This paper proposes an ultra-low power Bandgap Reference (BGR) operating in the subthreshold region. The proposed design contains no resistors and operates at a supply voltage below 1V. The BGR circuit consists of a biasing circuit, a Proportional to Absolute Temperature (PTAT) generator and a Complementary to Absolute Temperature (CTAT) generator based on diode-connected MOSFET. The PTAT generator is based on the Self- Cascode MOSFET (SCM) structure. The circuit was designed and simulated in a standard 90nm CMOS process. The circuit produces an output reference of 397.6mV at 27°C with a supply voltage of 0.9V. The BGR operates over a temperature range of -50°C to 80°C with a temperature coefficient(TC) of 16ppm/°C. The circuit consumes a power of 20.781nW.

The state-of-the-art is the commercial wireless capsule endoscope product, the PillCam capsule, developed by Given Imaging Ltd. The PillCam capsule transmits the GI images at the resolution of 256-by-256 8-bit pixels and the frame rate of 2 frames/sec (or fps). The PillCam has been successfully utilized to diagnose diseases of the small intestine and alleviate the discomfort and pain of patients. However, based on clinical experience; the PillCam still has some drawbacks. First, the PillCam cannot control its heading and moving direction itself. This drawback may cause image oversights and miss a disease. Second, the res- olution of demosaicked image is still low, and some inter- esting spots may be unintentionally omitted. Especially, the images will be severely distorted when physicians zoom images in for detailed diagnosis. The first drawback is the nature of passive endoscopy. Some papers have pre- sented approaches for the autonomous moving function [5,6]. Very few papers address the solutions of the second drawback. Increasing resolution may alleviate the second problem; however, it would result in significant power consumption in RF transmitter. Hence, applying image compression is necessary for saving the power dissipation of RF transmitter. The paper [11] provides a thorough review on GI image compression and motivated our research. To overcome the second drawback, we have been developing a new capsule endoscope, called GICam. Fig. 1 illustrates the system diagram of the proposed cap- sule endoscope. We attached an ultra-low-power image compressor to the CMOS sensor to deliver a compressed 512-by-512 image while the RF transmission rate is at 2 megabits per second. To reduce the buffer size between the CMOS sensor and the image compressor, the scanline

The proposed 8T SRAM cell can be very useful for ultra-low power applications operating voltage of 0.1V with reduced delay. The con- ventional 8T SRAM cell is modified in two ways to optimize power and delay. First, 8T with Read assist technique and second, 8T SRAM using two Extra pass transistors. These results are compared with Standard 6T SRAM and Conventional 8T SRAM cells. The delay of the proposed 8T SRAM with Read assist is reduced by 81.89% compared to 6T SRAM cell and reduced by 71.36% com- pared to Conventional 8T SRAM cell. The delay of the proposed 8T SRAM using two Extra pass transistors is reduced by 43.14% compared to 6T SRAM cell and reduced by 9.93% compared to Conventional 8T SRAM cell. The power of the proposed 8T SRAM with Read assist is reduced by 34.5% compared to 6T SRAM cell and reduced by 30.71% compared to Conventional 8T SRAM cell. The power of the proposed 8T SRAM using two Extra pass transis- tors is reduced by 44.42% compared to 6T SRAM cell and reduced by 41.20% compared to Conventional 8T SRAM cell. The ELDO simulation tool is used to verify these circuits. The schematic cir- cuits and layouts are designed with the help of Mentor Graphics– a laboratory software tool.

ABSTRACT: This paper proposes a characteristic of adiabatic logic in week inversion the transistor is also called sub threshold adiabatic logic (SAL). Operation of Half adder and Full adder is considered in this work. This proposed system is used for ultra low power on application. Comparison shows power analysis of existing with proposed one gives that reduced average power. The proposed system can save adequate energy by using the SAL CMOS implementation. Observations are validated through the extensive simulation in 180nm CMOS technology using HSPICE.

Custom CMOS vision sensors could offer large opportunities for ultra-low power applications, introducing novel visual computation paradigms, aimed at closing the large gap between vision technology and energy-autonomous sensory systems. Energy-aware vision could offer new opportunities to all those applications, such as security, safety, environmental monitoring and many others, where communication infrastructures and power supply are not available or too expensive to be provided, This thesis aims at demonstrating this concept, exploiting the potential of an energy- aware vision sensor, developed at FBK, that extracts the spatial contrast and delivers compressed data. As a case study, a custom stereo-vision algorithm has been developed, taking advantage of the sensor characteristics, targeted to a lower complexity and reduced memory with respect to a standard stereo-vision processing. Under specific conditions, the proposed approach has proven to be very promising, although much work has still to be done both at sensor and at processing levels.The last part of this thesis is focused on the improvement of the custom sensor. A novel vision sensor architecture has been developed, which is based on a proprietary algorithm, developed by a partner of FBK and targeted to surveillance applications. The algorithm is based on adaptive temporal contrast extraction and is very suitable to be implemented at chip level. Although the output of the algorithm has strong similarities with the spatial contrast vision sensor, it relies on temporal contrast rather than spatial one, which is much more robust for event detection applications. A first prototype of ultra-low power adaptive temporal contrast vision sensor has been developed and tested.

current mirrors [3, 9-16]. Nevertheless, each work has its own drawbacks. For instance, [10] fails to operate in low voltage, [11] has a limited tuning range, and [3] suffers from low frequency bandwidth. In [9, 13, 14] the level shifters, and in [15] the floating gate transistors are used to achieve the gain tuning function. Also these techniques are promising, however, the presence of level shifters in signal path leads to increased power supply and decreased frequency bandwidth. On the other hand, the floating gate devices are commonly available in double-poly fabrication processes. The power consumption in [12] has been decreased, however, its tuning range and frequency bandwidth are very limited [16] deliver wide tuning range, but it works with a high supply voltage that is not suitable for low voltage and low power applications. In the all of the mentioned circuits, in order to adjust the gain, the operating current or voltages of circuits are varied significantly. However, these kinds of adjusting gain methods are not suitable for high performance applications that require ultra-low power consumption. In this paper, a very low voltage, low power, zero- pole reposition based VGCM structure is presented which delivers very small power consumption variation in all-over the gain tuning range. The proposed technique enables the structure to deliver some ever interesting features of low power consumption, wide programmable gain range, and acceptable frequency bandwidth. On the other hand, the bandwidth of proposed structure can simply be tuned as well.

The design of the proposed LDO circuit is consisting of a bandgap reference, error amplifier and a pass device. A low power LDO topology is investigated and utilized in this proposed work to achieve low quiescent current and leading to high power efficiency design of LDO. The design considerations of each building blocks in the LDO circuit is considered to realize an ultra-low power LDO design. The LDO is designed and simulated using Synopsys tool. The LDO design will be for the use of device level in an IoT device. Finally, the design is completed until layout design that is ready for fabrication.

A typical application for public-key cryptography in the ultra low-power domain is for Wireless Sensor Network (WSN). A WSN is an ad-hoc wireless network that consists of a number of nodes and one or more base stations. WSNs require security, because they communicate through an insecure communication medium and they often operate unattended. As these devices are made to be economically viable, they have a limited amount of energy, computation power, memory and communication abilities. A node’s lifetime is also directly influenced by the amount of energy that it uses to perform computations and is therefore also directly influenced by the efficiency of its algorithms.

Abstract— In this work, implementation of all the basic logic gates is presented using 180nm CMOS technology with a very low voltage of 0.7V. Ideally logic family should not dissipate power, have zero propagation delay, controlled rise and fall times with noise immunity. The property of CMOS closely approaches these characteristics. Another desirable characteristic of CMOS are its robustness with respect to voltage and size scaling. Though with all the desirable characteristics of CMOS when it is implemented in the field of VLSI design there is always a tradeoff between area, power dissipation and speed of operation. The main objective of this paper is to implement all the basic logic gates by exploiting the property of voltage and Gate size scaling of CMOS with ultra low power dissipation without affecting the normal operation of the basic gates. In IC technology which is powered by battery, if the total power dissipation is low, the service time offer by the battery is much longer.

Abstract: Power consumption is considered as one of the important challenge in modern VLSI design along with area and speed consideration. Flip flop plays very important role in digital systems. In this paper comparative study of four different flip flops which includes pulse triggered as well as conditional technique flip flop such as IP-DCO, MHLFF, CPSFF, and CPFF topologies in sub threshold operation are examined. In recent years the ultra low power application can be possible using sub threshold technology. Using the advantage of this technology the power consumption of these flip flops is minimized. Sub threshold circuit consume less power than strong inversion circuit at the same frequency. Design is done using HSPICE in TSMC 180nm technology. The flip flops are analysed in all corners and parameters such as delay, power delay product, Energy delay product, and average power is measured at power supply voltage 300mV, and applied clock frequency is 1 MHz at temperature of 27 0 C

In RFID application, a voltage regulator circuit with simple structure and low power dissipation is needed for low voltage operation. Switching regulators operate with higher efficiency than linear regulators at high power applications, because the former converts power while the latter wastes power. However, switching regulators consume more power at ultra low power applications, because an extra clock signal is required and it requires inductance which is very area consuming, such that, they are not desired for low power operation [10]. In linear regulators, shunt voltage regulators have only small sensitivity to variations of the supply voltage, and they have undesired current flowing through shunt resistors. Therefore, Due to the ultra-low-power and low-cost condition, series voltage regulators, so called low-dropout (LDO) regulator, is suitable as power management circuit for RFID operation.

The proliferation of applications that handle sensitive user data on wearable platforms generates a critical need for embedded systems that offer strong security without sacrificing flexibility and long battery life. To secure sen- sitive information, such as health data, ultra-low-power wearables must isolate applications from each other and protect the underlying system from errant or malicious application code. These platforms typically use micro- controllers that lack sophisticated Memory Management Units (MMU). Some include a Memory Protection Unit (MPU), but current MPUs are inadequate to the task, leading platform developers to software-based memory- protection solutions. In this paper, we present our memory isolation technique, which leverages compiler inserted code and MPU-hardware support to achieve better run- time performance than software-only counterparts.

In this work we fabricate and experimentally investigate ENZ metamaterials composed of metal-dielectric multilayers. We observe ultrafast nonlinear response of our structures at the red edge of the visible spectrum. The effective nonlinearity turns out to be one order of magnitude higher than that of the constituent materials of the equivalent thickness. At the same time the observed absorption losses are about one order of magnitude lower than absorptions of a silver layer of the same thickness as our sample. In this way we overcome the fundamental limitations related to the relatively low nonlinear response of natural materials. This is an extremely desirable property for many applications in fundamental studies ranging from ultrashort pulse generation and compression, higher harmonic generation and quantum optics, to more practical applications, such as all-optical switching and memory elements and other ultra-low power optical systems.

This paper explains the successful implementation of a simplex communication model that operates on Morse code using an ultra-low power MSP430F5529 Microcontroller. Text messages could be easily sent from one device to another at high speeds. Using Morse code ensures high security as only a skilled person can decode it. So, the efforts of any intruder tapping the message will be unsuccessful. On the contrary, the decoder which is designed enables the intended receiver to obtain the decoded message without efforts as it is automatically translated. This method of communication has got dual benefit of good bandwidth efficiency and low transmission power as compared to the other complex coding schemes. Also, using the MSP430 microcontroller with its wide range of LPM (Low Power Modes) reduces the power even more. It is comparatively more immune to interference, both natural and man-made. It has a great scope in the fields of aviation to communicate with the base station, in navy to communicate with different ships, radio communication like the Amateur Radio etc. Recently it has proved to be an important communication tool for the people with various disabilities to communicate. [4]

Abstract: In this paper, an ultra-low-power low-noise amplifier (LNA) at 5GHz is proposed. The main focus is on precise computation of output impedance, input impedance, and gain of the LNA. The LNA is composed of a common-source LNA and a cascode LNA. In fact, the casode LNA can assist to have more stability by declining S12 considerably. Plus, it can be beneficial via increasing the gain of the second stage of the final LNA. In addition, in order to emphasize the significance of the meticulous calculations, the formulas calculated in this paper are compared with their counterparts in other papers. The combination of two different supply voltage is mentioned as an approach to bring down the power dissipation of the circuit. Simulation is performed by MATLAB, HSPICE, and Advanced Design System (ADS). TSMC 0.18 um CMOS process is used to evaluate the circuit. The LNA is analyzed with two different voltage supply 0.7 V and 0.9 V. The input matching (S11) is -14 dB and -16 dB for voltage supply 0.7 V and 0.9 V respectively. Plus, power dissipation, noise figure (NF), and gain (S21) are 532 µW, 944 µW, 1.25 dB, 1.05dB, 15dB, and 17dB for voltage supply 0.7 V and 0.9 V respectively.

ABSTRACT: Power and area are the two major concerns in design of any digital circuit. At present scenario low power device design and its implementation have got a significant role in the field of nano electronics. However much research not has been done at ultra-low power with acceptable performance and high performance design with power. To achieve the ultra-low power requirement is to operate the digital logic gates in subthreshold region. This paper investigates the analysis of CMOS technology in 45 nm channel length where the relative study of average power dissipation of CMOS inverter. We analyze and compare CMOS Inverter and other logic gates in subthreshold region. The subthreshold current is found to be exponentially related to the gate voltage. Thus,this exponential relationship not only gives an exponential reduction in power consumption, but also an exponential increase in delay. The simulation results are taken at 45nm using CMOS technology with the help of Cadence tool. The simulation results show that the reduction in power outweighs the increase in propogation delay.

Abstract: In this paper, a new approach is proposed for designing ultra-low-power FFT (Fast Fourier Transform) system suitable for use in energy harvesting powered sensors. Bit-serial architecture is adopted to reduce the power consumption of butterfly operation. Simulation results show that, compared with state-of-the-art bit-serial and conventional parallel processors, the proposed technique is superior in terms of silicon area, power consumption, dynamic energy use due to variable precision arithmetic. A sample design of a 64-point FFT shows that the implementation can save about 40% area and 36% leakage power compared with a conventional parallel counterpart, accordingly achieving significant power benefits at a low sample rate and low voltage domain. The dynamic variation of the arithmetic precision can be achieved through a simple modification of the controller with hardware area overhead of 10% gate count.

Ever-growing demand for portability and increased performance has resulted in increased levels of dissipated power in digital circuits. This poses a threat to the rate of advancement of the electronics industry. Use of adiabatic technology is one key solution to curb the growing power needs. Adiabatic circuits significantly reduce the dynamic power dissipation of a circuit, thus reducing the overall power [1-2]. Operating digital circuits in the sub-threshold region is another way to reduce dissipated power to sufficiently low levels. Circuits operating in the sub-threshold region use leakage currents for realizing the logic. Thus dissipated power dominantly comprises of the leakage power [3-7]. Both these techniques have great potential yet to be exploited.This paper attempts to combine the advantages offered by the adiabatic logic family and subthreshold operation to design ultra low power digital circuits. Adiabatic circuits when operated within the sub-threshold region can reduce both dynamic as well as static power thus greatly reducing the overall power dissipation. Two different adiabatic logic families have been discussed and successfully operated within the sub-threshold region.

It can be also used many kind of implementations from various different authors, but this generators will every time generate only pseudo-random combinations of numbers [13] and from basic description of PRGN is evident it have bigger requirements for memory or energy compare to hardware generators, which use for generating physical events and not mathematical apparatus . This is big disadvantages for ultra-low-power devices and also the reason for choosing some hardware solution. When the generator is used in practical situations ( devices) it is also necessary to count the final price. When it will be used some external module, it is evident the final price will grove and also reason for using internal modules (if it is possible).