Let’s look at a model that looks correct at first glance, but does not function as the user intended. The model is for the 4 to 1 multiplexer discussed earlier:
USE WORK.std_logic_1164.ALL; ENTITY mux IS
PORT (i0, i1, i2, i3, a, b: IN std_logic; PORT (q : OUT std_logic);
END mux;
ARCHITECTURE bad OF mux IS BEGIN
q <= i0 WHEN a = ‘0’ AND b = ‘0’ ELSE ‘0’; q <= i1 WHEN a = ‘1’ AND b = ‘0’ ELSE ‘0’; q <= i2 WHEN a = ‘0’ AND b = ‘1’ ELSE ‘0’; q <= i3 WHEN a = ‘1’ AND b = ‘1’ ELSE ‘0’; END BAD;
This model assigns i0to qwhen ais equal to a 0 and bis equal to a 0; i1when ais equal to a 1 and bis equal to a 0; and so on. At first glance, the model looks like it works. However, each assignment to signal qcreates a new driver for signal q. Four drivers to signal qare created by this model. Each driver drives either the value of one of the i0, i1, i2, i3inputs or ‘0’. The value driven is dependent on inputs aand b. If ais equal to ‘0’and bis equal to ‘0’, the first assignment statement puts the value of i0into one of the drivers of q. The other three assignment statements do not have their conditions met and, therefore, are driving the value ‘0’. Three drivers are driving the value ‘0’, and one driver is driving the value of i0. Typical resolution functions would have a difficult time predicting the desired output on q, which is the value of i0.
A better way to write this model is to create only one driver for signal q, as shown in the following:
ARCHITECTURE better OF mux IS BEGIN
q <= i0 WHEN a = ‘0’ AND b = ‘0’ ELSE i1 WHEN a = ‘1’ AND b = ‘0’ ELSE i2 WHEN a = ‘0’ AND b = ‘1’ ELSE i3 WHEN a = ‘1’ AND b = ‘1’ ELSE ‘X’; --- unknown
END better;
Generics
Generics are a general mechanism used to pass information to an instance of an entity. The information passed to the entity can be of most types allowed in VHDL. (Types are covered in detail later in Chapter 4, “Data Types.”)
Why would a designer want to pass information to an entity? The most obvious, and probably most used, information passed to an entity is delay times for rising and falling delays of the device being modeled. Generics can also be used to pass any user-defined data types, including information such as load capacitance, resistance, and so on. For synthesis parameters such as datapath widths, signal widths, and so on, can be passed in as generics.
All of the data passed to an entity is instance-specific information. The data values pertain to the instance being passed the data. In this way, the designer can pass different values to different instances in the design.
The data passed to an instance is static data. After the model has been elaborated (linked into the simulator), the data does not change during simulation. Generics cannot be assigned information as part of a simula- tion run. The information contained in generics passed into a component instance or a block can be used to alter the simulation results, but results cannot modify the generics.
The following is an example of an entity for an AND gate that has three generics associated with it:
ENTITY and2 IS
GENERIC(rise, fall : TIME; load : INTEGER); PORT( a, b : IN BIT;
PORT( c : OUT BIT); END AND2;
delays, as well as the loading that the device has on its output. With this information, the model can correctly model the AND gate in the design. Following is the architecture for the AND gate:
ARCHITECTURE load_dependent OF and2 IS SIGNAL internal : BIT;
BEGIN
internal <= a AND b;
c <= internal AFTER (rise + (load * 2 ns)) WHEN internal = ‘1’ ELSE internal AFTER (fall + (load * 3 ns));
END load_dependent;
The architecture declares a local signal called internalto store the value of the expression aand b. Pre-computing values used in multiple instances is a very efficient method for modeling.
The generics rise, fall, and load contain the values that were passed in by the component instantiation statement. Let’s look at a piece of a model that instantiates the components of type AND2 in an- other model:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY test IS
GENERIC(rise, fall : TIME; load : INTEGER); PORT ( ina, inb, inc, ind : IN std_logic; PORT ( out1, out2 : OUT std_logic); END test;
ARCHITECTURE test_arch OF test IS COMPONENT AND2
GENERIC(rise, fall : TIME; load : INTEGER); PORT ( a, b : IN std_logic;
PORT ( c : OUT std_logic); END COMPONENT;
BEGIN
U1: AND2 GENERIC MAP(10 ns, 12 ns, 3 ) PORT MAP (ina, inb, out1 );
U2: AND2 GENERIC MAP(9 ns, 11 ns, 5 ) PORT MAP (inc, ind, out2 );
END test_arch;
The architecture statement first declares any components that will be used in the model. In this example, component AND2is declared. Next, the body of the architecture statement contains two of the component instan- tiation statements for components U1and U2. Port aof component U1is mapped to signal ina, port bis mapped to signal inb, and port cis mapped
to out1. In the same way, component U2is mapped to signals inc, ind, and out2.
Generic rise of instance U1 is mapped to 10 nanoseconds, generic fallis mapped to 12 nanoseconds, and generic loadis mapped to 3. The generics for component U2 are mapped to values 9 and 11 nanoseconds and value 5.
Generics can also have default values that are overridden if actual values are mapped to the generics. The next example shows two instances of component type AND2.
In instance U1, actual values are mapped to the generics, and these values are used in the simulation. In instance U2, no values are mapped to the instance, and the default values are used to control the behavior of the simulation if specified; otherwise an error occurs:
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; ENTITY test IS
GENERIC(rise, fall : TIME; GENERIC(load : INTEGER);
PORT ( ina, inb, inc, ind : IN std_logic; PORT ( out1, out2 : OUT std_logic);
END test;
ARCHITECTURE test_arch OF test IS COMPONENT and2
GENERIC(rise, fall : TIME := 10 NS; GENERIC(load : INTEGER := 0); PORT ( a, b : IN std_logic; PORT ( c : OUT std_logic); END COMPONENT;
BEGIN
U1: and2 GENERIC MAP(10 ns, 12 ns, 3 ) PORT MAP (ina, inb, out1 );
U2: and2 PORT MAP (inc, ind, out2 );
END test_arch;
As we have seen, generics have many uses. The uses of generics are limited only by the creativity of the model writer.