The signal assignment statement is the most basic form of behavioral modeling in VHDL. Following is an example:
a <= b;
This statement is read as follows: agets the value of b. The effect of this statement is that the current value of signal bis assigned to signal a. This statement is executed whenever signal bchanges value. Signal b is in the sensitivity list of this statement. Whenever a signal in the sen- sitivity list of a signal assignment statement changes value, the signal assignment statement is executed. If the result of the execution is a new value that is different from the current value of the signal, then an event is scheduled for the target signal. If the result of the execution is the same value, then no event is scheduled but a transaction is still generated (transactions are discussed in Chapter 3, “Sequential Processing”). A trans- action is always generated when a model is evaluated, but only signal value changes cause events to be scheduled.
The next example shows how to introduce a nonzero delay value for the assignment:
a <= b after 10 ns;
This statement is read as follows: a gets the value of b when 10 nanoseconds of time have elapsed.
Both of the preceding statements are concurrent signal assignment state- ments. Both statements are sensitive to changes in the value of signal b. Whenever bchanges value, these statements execute and new values are assigned to signal a.
Using a concurrent signal assignment statement, a simple AND gate can be modeled, as follows:
ENTITY and2 IS
PORT ( a, b : IN BIT; PORT ( c : OUT BIT ); END and2;
ARCHITECTURE and2_behav OF and2 IS BEGIN
A
B
C
Figure 2-1
AND Gate Symbol.
END and2_behav;
The AND gate has two inputs a, band one output c, as shown in Figure 2-1. The value of signal cmay be assigned a new value whenever either aor bchanges value. With an AND gate, if ais a ‘0’and bchanges from a ‘1’to a ‘0’, output cdoes not change. If the output does change value, then a transaction occurs which causes an event to be scheduled on signal c; otherwise, a transaction occurs on signal c.
The entity design unit describes the ports of the and2gate. There are two inputs aand b, as well as one output c. The architecture and2_behav for entity and2contains one concurrent signal assignment statement. This statement is sensitive to both signal aand signal b by the fact that the expression to calculate the value of cincludes both aand bsignal values. The value of the expression aand bis calculated first, and the resulting value from the calculation is scheduled on output c, 5 nanoseconds from the time the calculation is completed.
The next example shows more complicated signal assignment state- ments and demonstrates the concept of concurrency in greater detail. In Figure 2-2, the symbol for a four-input multiplexer is shown.
This is the behavioral model for the mux: LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY mux4 IS
PORT ( i0, i1, i2, i3, a, b : IN std_logic; PORT ( i0, i1, i2, i3, a, q : OUT std_logic); END mux4;
ARCHITECTURE mux4 OF mux4 IS SIGNAL sel: INTEGER;
BEGIN
WITH sel SELECT
q <= i0 AFTER 10 ns WHEN 0, q <= i1 AFTER 10 ns WHEN 1,
I0 I1 A B Q MUX4 I3 I2 Figure 2-2 Mux4 Symbol. q <= i2 AFTER 10 ns WHEN 2, q <= i3 AFTER 10 ns WHEN 3, q <= ‘X’ AFTER 10 ns WHEN OTHERS;
sel <= 0 WHEN a = ‘0’ AND b = ‘0’ ELSE 1 WHEN a = ‘1’ AND b = ‘0’ ELSE 2 WHEN a = ‘0’ AND b = ‘1’ ELSE 3 WHEN a = ‘1’ AND b = ‘1’ ELSE 4 ;
END mux4;
The entity for this model has six input ports and one output port. Four of the input ports (I0, I1, I2, I3) represent signals that will be assigned to the output signal q. Only one of the signals will be assigned to the out- put signal qbased on the value of the other two input signals aand b. The truth table for the multiplexer is shown in Figure 2-3.
To implement the functionality described in the preceding, we use a conditional signal assignment statement and a selected signal assignment. The second statement type in this example is called a conditional signal assignment statement. This statement assigns a value to the target sig- nal based on conditions that are evaluated for each statement. The statement WHENconditions are executed one at a time in sequential order until the conditions of a statement are met. The first statement that matches the conditions required assigns the value to the target signal. The target signal for this example is the local signal sel. Depending on the values of signals a and b, the values 0 through 4 are assigned to sel.
A B Q 0 0 I0 1 0 I1 0 1 I2 1 1 I3 Figure 2-3 Mux Functional Table.
matches does the assign, and the other matching statements’ values are ignored.
The first statement is called a selected signal assignment and selects among a number of options to assign the correct value to the target sig- nal. The target signal in this example is the signal q.
The expression (the value of signal selin this example) is evaluated, and the statement that matches the value of the expression assigns the value to the target signal. All of the possible values of the expression must have a matching choice in the selected signal assignment (or an OTHERS clause must exist).
Each of the input signals can be assigned to output q, depending on the values of the two select inputs, aand b. If the values of aor bare unknown values, then the last value, ‘X’ (unknown), is assigned to output q. In this example, when one of the select inputs is at an unknown value, the out- put is set to unknown.
Looking at the model for the multiplexer, it looks like the model will not work as written. It seems that the value of signal selis used before it is computed. This impression is received from the fact that the second statement in the architecture is the statement that actually computes the value for sel. The model does work as written, however, because of the concept of concurrency.
The second statement is sensitive to signals aand b. Whenever either aor bchanges value, the second statement is executed, and signal selis updated. The first statement is sensitive to signal sel. Whenever signal selchanges value, the first signal assignment is executed.
If this example is processed by a synthesis tool, the resulting gate structure created resembles a 4 to 1 multiplexer. If the synthesis library contains a 4 to 1 multiplexer primitive, that primitive may be generated
based on the sophistication of the synthesis tool and the constraints put on the design.