Simulation deltas are used to order some types of events during a simu- lation. Specifically, zero delay events must be ordered to produce con- sistent results. If zero delay events are not properly ordered, results can be disparate between different simulation runs. An example of this is shown using the circuit shown in Figure 2-6. This circuit could be part of a clocking scheme in a complex device being modeled. It probably would not be the entire circuit, but only a part of the circuit used to generate the clock to the D flip-flop.
The circuit consists of an inverter, a NAND gate, and an AND gate driving the clock input of a flip-flop component. The NAND gate and AND gate are used to gate the clock input to the flip-flop.
Let’s examine the circuit operation, using a delta delay mechanism and another mechanism. By examining the two delay mechanisms, we will better understand how a delta delay orders events.
D CLK Q QB DFF A Clock C D B E F Figure 2-6 Simulation Delta Circuit.
To use delta delay, all of the circuit components must have zero delay specified. The delay for all three gates is specified as zero. (Real circuits do not exhibit such characteristics, but sometimes modeling is easier if all of the delay is concentrated at the outputs.) Let’s examine the non- delta delay mechanism first.
When a falling edge occurs on signal A, the output of the inverter changes in 0 time. Let’s assume that such an event occurs at time 10 nanoseconds. The output of the inverter, signal B, changes to reflect the new input value. When signal B changes, both the AND gate and the NAND gate are reevaluated. For this example, the clock input is assumed to be a constant value ‘1’. If the NAND gate is evaluated first, its new value is ‘0’.
When the AND gate evaluates, signal B is a ‘0’, and signal C is a ‘1’; therefore, the AND gate predicts a new value of ‘0’. But what happens if the AND gate evaluates first? The AND gate sees a ‘1’value on signal B, and a ‘1’ value on signal C before the NAND gate has a chance to reevaluate. The AND gate predicts a new value of ‘1’.
AND First NAND First
evaluate inverter evaluate inverter
B <= 1 B <= 1
evaluate AND (C = 1) evaluate NAND
D <= 1 C <= 0
evaluate NAND evaluate AND
C <= 0 D <= 0 evaluate AND D <= 0 Figure 2-7 Comparison of Two Evaluation Mecha- nisms.
The NAND gate reevaluates and calculates its new value as ‘0’. The change on the output of the NAND gate causes the AND gate to reevaluate again. The AND gate now sees the value of B, a ‘1’value, and the new value of signal C, a ‘0’value. The AND gate now predicts a ‘0’on its output. This process is summarized in Figure 2-7.
Both circuits arrive at the same value for signal D. However, when the AND gate is evaluated first, a rising edge, one delta delay wide, occurs on signal D. This rising edge can clock the flip-flop, depending on how the flip-flop is modeled.
The point of this discussion is that without a delta synchronization mechanism, the results of the simulation can depend on how the simulator data structures are built. For instance, compiling the circuit the first time might make the AND gate evaluate first, while compiling again might make the NAND gate evaluate first—clearly not desirable results; simu- lation deltas prevent this behavior from occurring.
The same circuit evaluated using the VHDL delta delay mechanism would evaluate as shown in Figure 2-8.
The evaluation of the circuit does not depend on the order of evalua- tion of the NAND gate or AND gate. The sequence in Figure 2-8 occurs irrespective of the evaluation order of the AND or NAND gate.
During the first delta time point of time 10 nanoseconds, signal A receives the value ‘0’. This causes the inverter to reevaluate with the new value.
Time Delta Activity 10 ns (1) A <= 0 evaluate inverter (2) B <= 1 evaluate AND evaluate NAND (3) D <= 1 C <= 0 evaluate AND (4) D <= 0 11 ns Figure 2-8
Delta Delay Evalua- tion Mechanism.
The inverter calculates the new value for signal B, which is the value ‘1’. This value is not propagated immediately, but is scheduled for the next delta time point (delta 2).
The simulator then begins execution of delta time point 2. Signal B is updated to a ‘1’value, and the AND gate and NAND gate are reevaluated. Both the AND gate and NAND gate now schedule their new values for the next delta time point (delta 3).
When delta 3 occurs, signal D receives a ‘1’value, and signal C receives a ‘0’value. Because signal C also drives the AND gate, the AND gate is reevaluated and schedules its new output for delta time point 4.
To summarize, simulation deltas are an infinitesimal amount of time used as a synchronization mechanism when 0 delay events are present. Delta delay is used whenever 0 delay is specified, as shown in the fol- lowing:
a <= b AFTER 0 ns;
Another case for using delta delay is when no delay is specified. For example:
a <= b;
In both cases, whenever signal bchanges value from an event, signal ahas a delta-delayed signal assignment to it.
An equivalent VHDL model of the circuit shown in Figure 2-6, except for the flip-flop, is shown in the following:
ENTITY reg IS
PORT( a, clock : in bit PORT( d : out bit); END reg;
ARCHITECTURE test OF reg IS SIGNAL b, c : bit;
BEGIN
b <= NOT(a); -- notice no delay c <= NOT( clock AND b);
d <= c AND b; END test;