A clock generator, also known as a frequency timing generator (FTG) or frequency synthe- sizer, is a device that uses a crystal, an oscillator or a given clock as an input, and can create a wide range of frequencies as an output. As an example: a 16-MHz crystal can be used as an input into the FTG and i,t in turn, generates an output of 14.31818 MHz. Even though the output frequency seems to have little in common with the input frequency, it can typically be created in an FTG with no deviation in frequency.
The benefit of an FTG, as discussed above, is allowing the user to configure the part to have numerous output configurations. This configurationcan be done just prior to installing it on the board, or after, allowing the utmost in versatility. All of these benefits do however come with several drawbacks, the most significant being increased phase noise or jitter. This is mostly an issue in communications standards, such as SONET, FibreChannel and Gigabit Ethernet, whose extremely high speeds dictate an extremely pure clock source. An additional item to note is whether the output must be in phase with the input frequency. Some FTG’s offer phase alignment for particular configurations only, while others do not offer this at all.
An FTG is made up of a divider (Q), phase detector (PD), charge pump (CP), voltage controlled oscillator (VCO), multiplier (P) and a post divider (N), as shown in Figure 12.2. This is essentially a PLL, as was discussed in Chapter 2, with the P, Q, and N dividers added.
Figure 12.2 Clock Generator Block Diagram
The Q counter takes the reference clock input and divides it prior to sending it into one of the phase detector inputs. The P counter takes the output of the VCO and divides it down before it is given as the feedback (FB) into the second phase detector input (effectively causing multiplication). The Phase Detector determines which input signal, the reference/Q (REF) or the feedback/P (FB), occurs first. It sends an up or down signal to the charge pump to align the two signals. If the feedback is slow, it will send an “up” to the charge pump. The charge pump monitors the Phase Detector output and either increases or decreases the reference voltage that it supplies to the VCO. The VCO looks at the control voltage from the charge pump and creates the corresponding frequency as its output. Increasing or decreasing the control voltage will increase or decrease the VCO frequency. The N counter (post divider) divides the output of the VCO prior to its output of the device. By adjusting the P, Q and N values, the output is created from the input frequency. Both Q and N are clock dividers (pre and post-divide,respectively) while P is the multiplication factor.
In the simplest case, assume that the P, Q and N dividers are all set to one. This device then functions as a zero delay buffer (Figure 12.3). The reference clock drives the REF input of the phase detector. The phase detector follows the rising edge of the REF signal and causes the charge pump to speed up or slow down the VCO so that the FB signal at its other input matches every REF rising edge with a corresponding FB rising edge. Since this is actually the VCO output, the VCO runs at the same frequency as the reference input. By matching the FB and output buffer path lengths within the device, the output of the device has zero skew (propagation delay) relative to its input.
Figure 12.3 Zero Delay Buffer (ZDB) Block Diagram
A more complex example is to generate the 14.31818-MHz output from a 16-MHz input. The values for P, Q and N are not one in this case and need to be calculated to get the desired result while not exceeding the limits of the VCO. The output frequency is a function
12 - 4 VCO CP PD FREF FVCO Up Down V FOUT VCO CP PD FB /P /N /Q FREF FVCO Up Down V FOUT
of the VCO divided by N. The VCO frequency is a function of the input clock and the P and Q ratio. These two relationships can be expressed with the following equations:
Output frequency = VCO frequency/N Input frequency/Q = VCO frequency/P
Combining them, the output frequency and ratios can be expressed with the following equations:
Output frequency = (Input Frequency/Q) * (P/N) Output frequency/Input Frequency = P/(N*Q)
For the example of a 16-MHz input generating a 14.318182 output, there is the following substitution:
14.31818/16.000000 = P/(N * Q) 0.89488652 = P/(N * Q)
By using the values of Q set to 44, P equal to 315 and N equal to 8, the phase detector has an input frequency of 45.45454 kHz and the VCO has a frequency of 114.545455 MHz. Both of these frequencies are within their operating limits of the particular device chosen for this example. The methods of how to calculate these numbers by hand as well as through software algorithms are discussed next.