Although SPICE is a comprehensive modeling and simulation environment, there are a few problems from a designer’s perspective. What may be the biggest drawback is the reluctance of integrated circuit manufacturers to release SPICE models for their devices. Due to its structural nature, a SPICE model must reveal many details of a device that manufacturers consider proprietary. The lack of readily available models often makes it difficult to use SPICE to validate circuit designs.
IBIS, (the Input/Output Buffer Information Specification), was created in 1993 by an industry-wide group of simulation experts to provide a standard method to exchange electrical component modeling data between integrated circuit manufacturers, simulation software vendors, and design engineers. This standard was developed and is maintained by regular “IBIS Open Forum” meetings that are held by the group. The latest approved version of the standard as of this writing is version 4.1 and is an official ANSI/EIA-656 and IEC 62014-1 standard. The official web site of the group is located at
http://www.eigroup.org/IBIS/.
In contrast to the structural models of SPICE, an IBIS model is a behavioral model. It is not defined by the structure of the component to be modeled but rather by the way it behaves. IBIS models contain data based on how the component acts or reacts within a circuit as it is tested or operated. This data takes the form of current-voltage (I-V) tables, edge waveforms, lumped capacitance, inductance, and resistances. This data can come from actual measurements or full circuit simulation. Since the model is based on how the device behaves and not on mathematical formulas, non-linear effects can also be included in the model. Although IBIS includes many analog characteristics, it is really a digital simulation tool. The stimulation performed by an IBIS driver is a logic transition with rising edges, falling edges, or a series involving both edges.
receivers for a single device or family of devices. Figure 10.3 shows the general input structure for an IBIS model. This includes the lumped package parasitics (capacitance, resistance, and inductance) and the Electric Static discharge (ESD) clamping structures and the capacitance of the input stage. The parasitics are specified as values while the ESD clamps are specified as I-V tables. Figure 10.4 shows the basic IBIS output structure. It contains the same basic structure as the input model with the addition of the behavior of the driver itself. These are specified as I-V tables and as voltage-time tables for rise-time /fall-time information.
Figure 10.3 IBIS Input Structure
Figure 10.4 IBIS Output Structure
There are three sets of possible values within an IBIS model. The values have different meanings depending on the context. In general, the “min.” values describe slow, weak behavior while the “max.” values describe fast, strong behavior. The “typ.” values refer to typical operating conditions. This behavior is determined by temperature and voltage extremes as well as manufacturing process tolerances. The conditions that cause a behavior may vary for different device families. For instance, a CMOS device will exhibit fast, strong behavior at low temperatures, while a bipolar device will exhibit this behavior at high temperatures. These conditions are also given in the model file.
1 0 - 4 C _comp C _Pkg L _Pkg R _Pkg Power _Clamp Ground _Clamp VCC Device Pin C _comp C _Pkg L _Pkg R _Pkg Power _Clamp Ground _Clamp VCC VCC Ramp Rising _Waveform Falling _Waveform Pullup Pulldown Device Pin
Version 1.0 of the IBIS specification defines a baseline model to which all IBIS-generated models must be backward compatible. Version 1.1 is a refined revision and is generally accepted as the first major release. Version 1.1 defines the input and output structures given in Figures 10.3 and 10.4. Parameters GND_Clamp, Power_Clamp and Pullup/ Pulldown information are provided in tables. Table 10.1 shows the first few lines of the Pulldown table for an IBIS model.
Table 10.1 IBIS Pulldown example
This is an I-V table that shows the current characteristics of the output stage of the device when the Pulldown is active and a specific voltage is applied to the output. The current in an I-V table is positive when the direction of the current is into the component. For the Pulldown and GND_Clamp, the table voltage is the actual voltage. Therefore, the first entry in Table 10.1 signifies a 2.09A current flow out of the device when a voltage of –3.3V is externally applied to the output pin. For the Pullup and Power_Clamp values, the table voltage is VCCrelative meaning that Voutput = VCC– Vtable. For instance, an entry of –3.3V
in a Pulldown table on a device with a VCCof 3.3V indicates an applied voltage of 6.6V on
the output pin. All devices must be characterized for an input voltage ranging from –VCC
to twice VCCalthough some table types are not required to span that entire range. This
range is ideal for determining the effects of transient overshoots and undershoots. Another important feature included in the first IBIS release is the Ramp specification. Ramp values show the rise and fall times for an output buffer. An example is shown in Table 10.2. Table 10.2 IBIS Ramp Values Example
In the Ramp table, the dV/dt_r is the rising edge and the dV/dt_f is the falling edge of the Ramp
Variable Typ. Min. Max.
dV/dt—r 1.75/1.45n 1.56/1.38n 1.95/1.49n dV/dt—r 1.78/1.53n 1.59/1.44n 1.98/1.59n R—load=50.00
Pulldown
Voltage I (typ.) I (min.) I (max.)
–3.30 –2.09A –2.12A –2.06
–3.10 –1.93A –1.96A –1.90A
–2.90 –1.76A –1.79A –1.73A
–2.70 –1.59A –1.63A –1.56A
–2.50 –1.43A –1.46A –1.40A
–2.30 –1.26A –1.30A –1.23A
–2.10 –1.10A –1.13A –1.07A
voltage swing. The lower number is the time this transition takes. As mentioned earlier, the min is the slow, weak behavior while the max is the fast, strong behavior. The resistive load for which this behavior is observed is also given in this section as the R_load parameter. The Ramp values include the intrinsic component capacitance but do not take into account the package parasitics.