We’ve covered the point-to-point single ended clock cases with the most common termination techniques, but what about multiple destinations? Ideally, clock signals should have a single source for every load device, but there are times when two or more loads may be required. We will look at several of the common scenarios and address the areas of concern.
Suppose we have two devices that we want to drive and both are very close physically to each other. There is only one clock driver output available and no option to add a larger buffer or second component. We also assume the trace is sufficiently long and therefore acts as a transmission line. We then have a single driver and a single trace with multiple loads as show in Figure 7.11.
If we use the Series termination method, RS is calculated as the difference between the
output impedance of the driver and the effective trace impedance. To prevent unwanted reflections from occurring due to the multiple loads, we must first analyze the stub length (which is the short trace segment between two separate destination loads) and signal rise time.
If the distance between the two loads is short, the two loads will act as one capacitive lumped load. However, if they are not, we will have an un-terminated stub and our signal will reflect at each point and result in multiple accepted and transmitted waves — basically, a poorly terminated trace. So the key question is how close do the loads need to be? That answer depends solely on the rise time of the driving signal. A good rule of thumb is: the length delay of the trace stub must be six times faster than the rise time of the signal. This guideline allows the transitioning signal to propagate up and down the stub rapidly enough to appear as a single pulse.
The rise time at this load will be different than a single load. If you recall from the earlier section with the single load, the rise time can be expressed as:
tR= 2.2 Z*C
Our capacitance has increased because there are two capacitive loads in parallel thus doubling the value of C. There is also additional trace capacitance because of the small stub connecting the two loads. Multiple loads at the end of the trace will work provided the stub is short and the rise time is still suitable for your application, as shown in Figure 7.12. However, it is always recommended to simulate your design.
Figure 7.12 Multiple Loaded Trace
Single Clock Driver (19.8 Output Impedance), 31.9-ohm Series Resistor, 6-inch Long Trace, 51.7 ohm Stripline (Effective), Two Loads 1-inch apart
Another common way to implement series termination driving two loads is to use two termination resistors and two separate traces, as shown in Figure 7.13.
This allows the loads to be physically far apart from each other with each segment termi- nated. The calculation for determining RSis a bit different from the single series termination
trace. In this case, we have the source driving a series resistor and trace impedance in parallel with another series resistor and trace. We can express this as:
RD+ RS1 || RS2 = ZO|| ZO
Notice when we add the second load, the trace impedance is halved since it is viewed in parallel. This results in the values of RSbeing less than the single trace termination. Note
that if the parallel trace impedance is less than the output driver impedance, the trace cannot be properly terminated. Let’s take a moment to review the wave propagation in the dual trace scenario. The driver will launch a signal with amplitude V into the trace. At the load side of the series termination resistors,1/
2V will begin to propagate down the trace.
Figure 7.13 Dual Traces
When the signal encounters the end, it will reflect back (the load will see V) propagating back towards the series termination resistor. Once encountered, some signal portion will be reflected and some will propagate beyond the resistor. To minimize continuing reflections, the overall trace lengths need to be equal in length. Also, the termination
RD RS ZO RS ZO Vertical: 1V/div Offset: –2.0V Horizontal: 1 ns/div Delay: 0.00 ns
resistors must be close to the source as given previously by the guideline in series terminated traces. If the trace lengths to the resistors have a flight time slower than one- tenth the rise time of the signal, this segment will act as a transmission line by itself. This will cause a reflection when the propagating signal encounters the resistors. This scenario is known as a bifurcated trace and should be avoided.
Care also needs to be exercised when selecting the clock driver. As each trace is added in parallel, the effective impedance is lowered. If this value is smaller than the output impedance of the clock driver, no value of RSwill be able to properly terminate the trace.
Therefore, select a driver with output impedance that will allow for termination. As in the case before, it is advisable to simulate the design with an IBIS or Spice simulator to verify the trace will perform as expected.