Today’s semiconductor manufacturing processes of digital integrated circuits mainly rely on complementary metal-oxide semiconductor (CMOS) technology. CMOS uses two types of metal-oxide-semiconductor field-effect transistor (MOSFET) devices, namely NMOS and PMOS transistors, that can basically be considered as voltage-controlled switches. NMOS and PMOS transistors are utilized to form standard cells in standard cell libraries [Nan10, Syn11] which are the foundation of contemporary semiconductor design. For more details on the structure and mechanics of transistors as well as the manufacturing processes and design of standard cells, the reader is referred to [WH11].
In modern semiconductor process technology nodes, conventional planar MOSFETs are being replaced by the recent fin-type field-effect transistor (FinFET) technology [HLK+00, Kin05, BC13]. The FinFET devices allow for scalable manufacturing of feature sizes be- yond 20nm, since they have a more compact layout with a faster switching behavior com- pared to traditional transistors [YMO15]. This enables the production of more complex
designs with higher transistor density that can be further run at higher clock frequencies to achieve even higher device performance. Although the physical structure of planar MOS- FET and FinFET is different, their basic working principles and design flows are similar.
2.1.1 CMOS Switching and Time Behavior
In today’s nanometer regime, it is often of utmost importance that the designs meet a certain performance requirement that is given by a minimum system clock frequency. The highest frequency a design can reliably run with is usually determined by the length of the critical path. The critical path accumulates all the propagation delays of standard cells and interconnects on the longest sensitizable path from a primary or pseudo-primary input to a primary or pseudo-primary output in the design.
In general, the delays of a standard cell are distinguished by propagation delays and rise/- fall times as shown in Fig. 2.1, which depicts the typical input and output waveform of a inverter cell in a small circuit (15nm FinFET technology [Nan14, BD15] powered with a supply voltage of 0.8V). The maximum signal amplitude on the left axis has been normal- ized. As shown, the signal switching processes do not occur instantly, but occur merely as a function of the voltage over time as a result of parametric and parasitic electrical elements in the circuit. The change of the voltage of a signal is typically modeled by differential equations that describe electrical charging and discharging processes of capacitances in the circuit [WH11]. 0 0.5 1 0 10 20 30 40 50 Signal [V] (normalized) time [ps] input output dr df dlh dhl 80% 20%
Figure 2.1: Rising/falling propagation delay (dr, df) and rise/fall times or slopes (dlh,dhl) of an INV_X1 CMOS inverter cell [Nan14, BD15]. (Adapted from [WH11])
The propagation delay is defined for rising (low-to-high) and falling (high-to-low) output transition polarities (dr and df) and describes the time it takes for a signal transition at a cell input to propagate to the cell output. It is measured from the time point where the input signal reaches the 50% mark of the maximum signal amplitude (i.e., 0.5 · VDD
2.1 CMOS Digital Circuits
as halfway between VDD and GND potential) to the point where the output crosses 50% of the maximum signal amplitude in response [WH11]. Moreover, as shown in Fig. 2.1, signal transitions are not instantaneous, but follow a certain continuous transition ramp or slope that are given by the rise-time dlh for rising and the fall-time dhlfor falling transitions as well. The rise-time (and fall time) of a signal transition is defined as the time it takes to transition from 20% to 80% of the maximum signal amplitude (and vice versa), though these thresholds can vary throughout the literature (e.g., 10%–90%) [WH11].
With the shrinking manufacturing process technologies and increasing complexity, it is important to accurately estimate the possible timing of contemporary and future designs. Thus, suitable models are required to reflect and consider CMOS-related timing effects as early and as accurately as possible during the design phase.
One approach to estimate the delay of a circuit is the RC delay model [WH11], which approximates the non-linear characteristics of transistors considering average resistances and capacitances of the circuit nodes. In the RC delay model, the circuit netlist is trans- formed into an electrical equivalent RC-circuit where all transistors and interconnects are replaced by simple resistors and the interconnect- and gate capacitances in the fanouts are replaced by (in the simplest case) lumped capacitances. A switching transistor causes a change in the state of the RC-model elements by changing the corresponding resistance. This triggers a transient at the output that is typically computed using the first-order or second-order step response [Elm48, WH11]. Hence, in case of the rising transient of Fig. 2.1 the step response vrise beginning at some time t0 can be modeled for the time t > t0 after as
vrise(t) := (GND − VDD) · e
−(t−t0)
τ +VDD, (2.1)
where τ is the time constant computed as τ := R · C, with R being the effective resistance of the driving PMOS transistor and C being the load capacitance. The propagation delay dr is then derived from the output signal vrise at the time it crosses 0.5 · VDD, which is computed as dr := τ · log 2[WH11]. Similarly, the falling transient vfall beginning at some time t1is calculated for t > t1 as
vfall(t) := (VDD − GND) · e
−(t−t1)
in which case the resistance R for the time constant τ := R · C corresponds to the effective resistance of the conducting NMOS transistor, resulting in an estimated falling propagation delay of df := τ · log 2. Both of the modeled rising and falling transients expressed by vrise and vfall are illustrated in Fig. 2.2. The axes have been normalized by τ for the time and by VDD for the voltage, respectively. For the sake of simplicity, it was assumed that the internal resistances of NMOS and PMOS were equal.
0 1 0 1 2 3 4 5 Output [V] (normalized) time [τ] τ log 2 0.5 vvrise fall 80% 20%
Figure 2.2: First-order step response for rising and falling transient modeling the continu- ous charging/discharging process of an output load capacitance. (Adapted from [WH11].)
2.1.2 Circuit Performance and Reliability Issues
With the shrinking feature sizes in newer technologies, the semiconductor manufactur- ing processes get more complex and increasingly prone to process variations and defects [SSB05, PBH+11]. Since the structures, such as fins of FinFET transistors, have a size of only a few nanometers, spot-defects by particles or statistical processes in the different manufacturing steps, such as dopant fluctuations, are getting more and more frequent and influential. These problems can severely alter the physical layout of the circuit structures and lead to improper connections in the design. Moreover, transistor-related parameters, such as the threshold voltage and electron mobility, can shift due to improper manufactur- ing. The resulting defects, such as open and shorts in either fins or gates [LX12], as well as variation artifacts [HTZ15] primarily impact the timing of the circuit [TTC+15, FGRC17] and ultimately affect the device performance and reliability by introducing delay faults. Certain parameter shifts in circuit structures exhibit small delays that sometimes indicate circuit aging or the presence of a marginal device [KCK+10]. For example, when a design is put under stress (i.e., high switching activity or mechanical stress) after deployment, struc- tures in the circuit can fail due to device degradation and transistor aging [BM09]. These wear-out mechanisms appear gradually as a result of continuing static and dynamic stress