Switch Level Waveform Representation

The switching process at a cell output from one voltage to another takes time due to vari- ous intrinsic and extrinsic capacitances (e.g., diffusion, wire and gate capacitances) which have to be charged or discharged over time [WH11]. The transient response behavior

of cells can be approximated with varying degree of accuracy. The response is typically calculated from differential equations over non-linear models [NP73] with stepwise eval- uation of the differential equations [CGK75]. Simplified models exist, with piecewise linear assumptions [Kao92], stepwise constant I/V characteristics [VR91], or piecewise exponential waveforms representing the first-order step response [BMA88] which make evaluations less complex at the sacrifice of accuracy.

Transient Response Modeling

In the RRC-cell model (cf. Fig. 6.3), the voltage at the output load capacitor Cload is considered as the output signal of the cell. In order to model a transient response, the first-order electrical parameters of the cell are reduced to a lumped RC low-pass equivalent circuit. The resulting RC circuit is composed of a lumped resistor that includes the effective driving resistance of the voltage divider (Ru, Rd) and the lumped interconnect resistance Rw ∈ R of the fanout, as well as the lumped output load capacitance Cload which can include diffusion and fanout gate capacitances. When a transistor device in an RRC-cell changes its state, the pull-up (Ru) or pull-down (Rd) resistance of the cell changes and hence the voltage divider ratio s (cf. Eq (6.3)) that determines the stationary voltage v. This causes the cell output capacitor Cload to (dis-)charge via the voltage divider from its current level to voltage v with the effective resistance Reff := (s · Ru), which delivers the time constant τ ∈ R which characterizes the transient response of the underlying RC circuit:

τ := (Reff + Rw) · Cload. (6.9)

Note, that only first-order electrical parameters are considered in the RRC-model while second-order capacitances (e.g., gate-source) are neglected. Hence, overshoots in the signal voltages due to trapping of charges are not modeled [WH11]. Therefore, given an arbitrary transistor switch at time ti ∈ R, the transient response of the RRC-cell output vo can be derived from Kirchhoff’s Current Law (KCL) following a monotonous [RPH83] exponential function vo(t)for time t ≥ ti:

6.2 Switch Level Circuit Model

where vo(ti) is the voltage at the capacitor Cload at the time ti and ∆t := (t − ti) is the elapsed time after the switch. The voltage vo(t)then strives asymptotically towards the stationary voltage v for t → ∞ and will saturate eventually.

Between any two consecutive transistor switches at times ti and ti+1, all resistances of transistors and nets in the RRC-cell, and hence the stationary voltage at the voltage divider, remain constant. Therefore, based on Eq. (6.11), the monotonous curve within each interval [ti, ti+1]of consecutive switches can be described entirely by a tuple composed of three parameters ei = (ti, vi, τi)assuming that the value vo(ti)at the beginning is known. Such a three-tuple will be referred to as a switch level event ei, whose components are:

• ti ∈ R: The time of the start of a new exponential curve expressed by the event eias a consequence of a transistor switch. This also marks the end of the previous segment (ei−1).

• vi ∈ R: The targeted stationary voltage of the new curve expressed by ei, which is derived from the resistances of the voltage divider, the supplying voltage VDD and ground voltage GND.

• τi ∈ R: The signal slope of the new curve segment of ei corresponding to the time constant calculated from the resistances at the voltage divider and the lumped load capacitance.

Fig. 6.4 shows the result of a SPICE transient analysis compared to the approximation of the signal with fitted ideal exponential curve segments. Compared to logic level time simulation, these curves approximate the electrical output behavior quite well and are able to contain sufficient information to express many of the delay effects found in CMOS.

Switch Level Waveform Modeling

The complete switching history of a signal over time is summarized as switch level wave- form similar to the data structure presented in Chapter 5. Each waveform is modeled by a list of temporally ordered events ˜w = {e1, e2, ..., ek} each of which stores the parameters of an exponential curve segment. This way, multiple continuous signal transitions can be modeled over time using a piecewise exponential approximation as depicted in Fig. 6.5.

0 0.3 0.8 1.1 0 20 40 60 80 Output [V] time [ps] U7_FIT U7_SPICEU4_FIT U4_SPICEU3_FIT U3_SPICE

a) 45nm PTM MOSFET technology [ZC06, Nan17]

0 0.2 0.6 0.8 0 5 10 15 20 Output [V] time [ps] U7_FIT U7_SPICEU4_FIT U4_SPICEU3_FIT U3_SPICE

b) 15nm PTM FinFET technology [MMR+_{15, Nan17]}

Figure 6.4: Signal transitions of cells from SPICE transient analysis with varying output load (dotted) and fitting with exponential functions (full strokes).

0 0.3 0.8 1.1 0 10 20 30 40 Signal W [V] time [a.u.] Signal W={(-∞, 0V, - ), (2.5, 1.1V, 1), (10, 0V, 4), (12, 0V, 2), (19, 0.55V, 4), (23, 1.1V, 4), (∞, - , - )} Event Waveform

Figure 6.5: Switch level event representation and visualization of an arbitrary signal. "Don’t care"-values are denoted by ’-’.

Besides the ordinary events, each waveform contains an initialization event (−∞, vinit, −) at the head of the list that marks a constant initial voltage vinit of a cell output (the latter ’−’ denotes a "don’t-care"-value). In addition, the event list is terminated by a termi- nation event (∞, −, −) with time t = ∞ as sentinel to indicate the end of the waveform data structure. The waveform signal is assumed to approach the stationary voltage v of the last ordinary event processed. Hence, fully detailed signal information is processed with smallest memory overhead, as no sampling of signal values is necessary, allowing for an efficient time- and value-continuous evaluation even for longer signal histories.

Each switch level waveform ˜wis evaluated by a switch level waveform function ˜w : R → R that delivers the voltage value present at the given point in time t ≥ 0 in the waveform ˜w.

6.3 Switch Level Simulation Algorithm

Following Eq. (6.10), the function is defined recursively as

˜ w(t) := ( ˜w(ti) − vi) · e− ∆t τi _{+ vi, (6.11)} with (ti, vi, τi) := max j∈N{(tj, vj, τj) ∈ ˜w|tj < t}, (6.12) where ˜w(ti) expresses the signal value at the time of the previous transient event ei := (ti, vi, τi) ∈ ˜win the waveform before t and ∆t := (t−ti)as the elapsed time in the current exponential curve segment.