The input to the algorithm is a levelized netlist G with each node being described at either logic or switch level, along with a set of input stimuli that are assigned to all primary and pseudo-primary inputs of the circuit stored in the waveform memory. The execution of the algorithm itself is performed again in topological order level by level from inputs to outputs and for each node the multi-level evaluation algorithm is called. The multi-level evaluation at a circuit node is outlined in Algorithm 8.1 [SKW18, SW19b].
Algorithm 8.1: Transparent multi-level simulation algorithm (single thread). Input: Node n, input waveforms wifor each input pin i ∈ I
Output: Event sequence of the output waveform wn
1 // Initialize local variables and data structures.
2 Create copy of node description and determine abstraction of node n. 3 // A. initialization
4 foreach node input i ∈ I do
5 Look-up abstraction level of input waveform wi.
6 Set-up corresponding data structures and determine initial waveform value vi.
7 Get first event eiof wiand put into event schedule E.
8 end
9 Compute initial state S of n and Initialize output waveform wn.
10 // B. event processing
11 while Events to process in schedule E do 12 // B.1 consume next event
13 Remove earliest event eifrom E.
14 if node n is ROI then
15 Transform eito switch level event and compute input value vi.
16 Compute new switch level state S of n.// switch level kernel 17 else
18 Transform eito logic level event and compute input value vi.
19 Compute new logic level state S of n.// logic level kernel 20 end
21 // B.2 output update
22 if S causes output change on n then 23 Compute output event and add to wn.
24 end
25 Get next event eiof input waveform wiand put into E.
26 end
27 // C. finalization
28 Append sentinel event at time ∞ to wn.
29 return Output waveform wn.
When a node n is processed, first the abstraction of the node is determined and the func- tional and timing description are loaded accordingly (line 2). Then the input waveform wi of each input i ∈ I of the current node n (line 4) are fetched and the abstraction level that is encoded in the header of each waveform wi is determined. Depending on the waveform
8.3 Transparent Multi-Level Time Simulation
type, the respective data structures for holding the current events of a waveform are set up as well as the initial waveform value of each waveform is calculated (line 4–8). The first event ei in each input waveform wi is fetched and put into the local event table E for scheduling, which keeps the immediate next event to be processed for each node in- put. After determining the initial signal value vi := wi(−∞)of each input waveform wi, the initial state S of the node output of n is determined and the output waveform wn is initialized (line 9). The initialization of the output waveform comprises the annotation of the abstraction level as well as writing the initial node output value of n corresponding to the computed initial state S.
The event processing loop (line 11–26) then processes all the events scheduled in the event table E in temporal order from earliest to latest. The earliest next event ei is con- sumed (line 13) by removing it from the schedule. Since each event eiindicates a change in the associated input signal value, the implications of the value change need to be trans- formed to the targeted abstraction level of the current node under evaluation. In case n is marked as a region of interest (ROI), the input signal value needs to be mapped to switch level (line 15) and the new switch level state of n is computed by calling the switch level evaluation kernel (line 16). Otherwise, the input signal is mapped to logic level (line 18) which is then processed using the logic level evaluation kernel (line 19).
If an input event eicauses a change in the output state of the cell, a new switching event e is appended to the output waveform wn (line 23), which is a switch level event in case n is marked as ROI and a logic level event, if otherwise. After the event has been processed, the next event of the current input waveform wi is fetched and scheduled into the event table E. The loop terminates when all events in the event table have been processed and the output waveform is terminated.
8.3.1 Waveform Transformation
The waveform transformation is performed by mapping the respective events from one abstraction level to representative events of the other type during simulation before they are put into the event schedule. This way at most one transformation per input waveform event is required at each node during the evaluation. If the abstraction level of an input
waveform matches the one of the node under evaluation, the event processing algorithm can proceed regularly without the need of explicit waveform transformation overhead. In the following, the two waveform transformations are explained in more detail.
Logic-to-Switch Level Transformation
Logic level waveforms are transformed to switch level by mapping the discrete logic value domain E3 to stationary voltages at switch level. Given the voltage levels of the power supply VDD and ground GND potential to represent high and low logic values, undefined values are mapped to the intermediate voltage level X → 12· (VDD + GND) [Hay86]. All events ei ∈ w of the original logic level waveform description are then translated by substituting each event ei = (ti)one after another by switch level events e0i. Based on the targeted logic value of a logic level event ei and a chosen time constant τε, the stationary voltage is selected as follows to obtain the switch level event e0
i: (ti) 7→ e0i := (t0i,VDD, τε) if (ti rising), (t0i,GND, τε) else if (ti falling), (t0i,12· (VDD + GND), τε) else, (8.2) where t0
i is the time of the new event e0i in the corresponding switch level waveform ˜w. The time t0i is computed according to Eq. (6.13), where the original ti is replaced by the new t0
i and the equation is solved for x = ti, such that the resulting curve segment of e0 crosses 12 · (VDD + GND) Volts at the time of the source logic level transition ti. For τε → 0, the shape of e0i closely resembles an instantaneous event with a steepness similar to transitions in the visualized logic level waveforms. The absolute error = |t0i− ti| of the resulting t0
i can be estimated by using Eq. (6.13), where t0i := ti− τε· log (0.5). Since for the last term | log(0.5)| < 1, it follows that the absolute error < τε. Thus, for very small τε → 0 the resulting curve is getting steeper and the shape is well expressing the logic level transition.
The RC-parameters of the input ports can be utilized to fit the curve segment of each resulting event e0
i := (t0i, v0i, τi0) by adjusting the time point t0i and the slope τi0 of the transition. Again, the curve parameters can be fitted using the log function in Eq. (6.13)
8.3 Transparent Multi-Level Time Simulation
to determine the time of an intersection with the threshold. According to the general definition of the output transition time [IEE01a], switches at logic level occur at a time point tiwhen the underlying signal at the electrical level passes the threshold at Vth= 12 · (VDD + GND) Volts (50% of VDD). Assuming a rising (falling) transition from a waveform value ˜w(ti) = GND (VDD) to the stationary voltage v0i = VDD (GND), the inner term of the log-function delivers
Vth− v0i ˜ w(ti) − v0i = 1 2· (VDD + GND) − v 0 i ˜ w(ti) − v0i = (VDD + GND) − 2 · v 0 i 2 · ( ˜w(ti) − v0i) (rising) =⇒ (VDD + GND) − 2 · VDD 2 · (GND − VDD) = −VDD + GND 2 · (−VDD + GND) = 1 2, (8.3) (falling) =⇒ (VDD + GND) − 2 · GND 2 · (VDD − GND) = VDD − GND 2 · (VDD − GND) = 1 2. (8.4)
Hence, from Eq. (8.3) for the rising transition and Eq. (8.4) for the falling transition parameters the inner log-term shortens to
Vth− v0i ˜
w(ti) − v0i = 1
2 = 0.5, (8.5)
which can be applied to Eq. (6.13) to finally determine the time t0i of a corresponding switch level curve with time constant τ0
i that crosses the 50% voltage threshold at the given intersection point ti:
ti= t! 0i− τi· log (0.5) =⇒ t0i := ti+ τi· log (0.5) .
This way, the transformed events can reflect the transient response over RC-elements in the circuit, which allows for a more realistic representations of the input waveforms at the current node under evaluation [SKW18].
Fig. 8.4 illustrates the transformation of a binary logic level waveform (”source”), for a small time constant τε := 10−5 (”τε trans.”) as well as for time-adjusted events based on RC-characteristics (”RC 50%”). As shown, the τε-curve overlaps the logic level repre- sentation without any noticeable error. In the latter case, the events exhibit the shape of exponential curves that cross the 50% voltage threshold at the exact times of the logic
level transitions. In addition, different RC-characteristics were chosen for the rising and falling transition, which resulted in different time offsets and slopes.
GND 50% VDD 0 10 20 30 40 50 60 70 80 Output [V] time [a.u.] source τ ε trans. RC 50%
Figure 8.4: Multi-level transformation of a logic level source waveform to switch level. The RC-characteristics vary for the rising and falling transition [SKW18].
Switch-to-Logic Level Transformation
For the switch level waveform transformation a threshold-based signal characterization from continuous voltage to discrete ternary logic values is applied based on Eq. (7.3). Two thresholds for low (VthL ∈ R) and high (VthH ∈ R) values are chosen to partition the voltage range [GND, VDD] ⊆ R into distinct intervals [GND, VthL), [VthL, VthH] and (VthH,VDD] each corresponding to the value range of a logic symbol in E3. The voltage intervals are assumed to be disjoint and in order to map each voltage value to a unique logic symbol such that
GND < VthL< 1
2 · (VDD + GND) < VthH <VDD. (8.6)
Algorithm 8.2 outlines the general switch to logic level transformation of a waveform. Starting from the initial waveform value v ∈ E3 at t = −∞ (line 1), the algorithm loops over the events of the switch level signal (line 5) as obtained from the event table in temporal order (cf. Chapter 6). Eq. (6.13) is used to determine possible intersection points within each of the curve segment. Each crossing of a threshold level VthL∈ R and VthH ∈ R at time ti then causes a change in the interpreted logic value v of the signal. Therefore the intersection points at times tican be directly mapped to corresponding logic level events. Again, for any transition to undefined, or from undefined to high state, the negative event time annotation is applied (line 8) in order to be compliant with the state transition diagram over the ternary logic E3 = {0, 1, X}(cf. Fig. 8.1).