8.2
Multi-Level Circuit Modeling
In the multi-level simulation, the circuit netlist is modeled as an abstraction-independent graph, which stores the general structure of the circuit including interconnections of the circuit nodes. For each node, abstraction-dependent functional and timing descriptions are assumed to be available for all abstraction levels. However, during simulation the description of only one abstraction level is used at a time per node. All output waveforms inherit the same abstraction level as their respective nodes.
In the following, the general approach for switching between different abstractions during simulation and the simulation flow is explained.
8.2.1 Region of Interest
The implemented multi-level simulation uses the concept of regions of interest (ROI) in order to switch abstraction levels in critical regions throughout the simulation [SKW18]. While the simulator is expected to run with the highest abstraction to maximize speed (logic level), nodes in the circuit netlist G can be activated to perform as ROI by assuming a lower abstraction level through swapping of their abstraction-dependent descriptions. Definition 8.2. A region of interest (ROI) is a connected sub-graph H ⊆ G of a netlist G with nodes of lower abstraction (switch level) compared to adjacent nodes.
The activation of ROIs at single or multiple nodes then allows to locally lower the ab- straction and gradually increase the modeling accuracy over the circuit. Different ROI activation schemes allow to change the accuracy during simulation:
• spots representing a single circuit node (e.g., standard cell),
• paths as sequence of nodes from an input to an output of the circuit,
• cones that cover a complete input or output cone, or cone of influence of a node, or • areas to model a connected sub-graph of the circuit netlist (e.g., module).
For example, ROI spots at single nodes can be utilized in order to introduce more accurate descriptions in case of complex-cells or injection-points for low-level fault modeling, which
otherwise would not be represented with sufficient accuracy at higher abstraction levels, or not represented at all. Paths can be activated, such as longest or critical paths required for investigation (i.e., paths that are likely to cause errors under a resistive open delay fault). ROI-cones enable provision of more accurate stimuli to a node and also enable low-level signal propagation to outputs. Similarly, the activation of ROI-areas lowers the abstraction in connected regions of the circuit (e.g., sub-module).
The multi-level circuit modeling can be utilized to simultaneously inject and simulate faults of mixed abstractions. When simulating a fault, it is injected into the node descrip- tion corresponding to the abstraction level of the fault. The node description with faults are then used actively during the simulation until the faults are removed. This way, all of the logic- and switch level fault models presented in Chapter 7 are supported.
8.2.2 Changing the Abstraction
When activating or removing a ROI in the netlist, the original netlist graph G = (V, E) is modified [MC95] in the process to generate a substitute graph G0 := (V0, E0)that includes the ROI. Let Vn⊆ V be a set of nodes of one abstraction connected to direct predecessors i ∈ I ⊆ V and direct successors o ∈ O ⊆ V in the graph such that (I ∪ O) ∩ Vn = ∅. All nodes n ∈ Vnare connected to the predecessors via edges Ei :=Si∈I{(i, n) ∈ E} and to the successors via Eo := S
o∈O{(n, o) ∈ E}. Further, let En := S
i,o∈Vn{(i, o) ∈ E} be the
set of edges that connect nodes internally in Vn. Then Gn:= (Vn, En∪ Ei∪ Eo)forms the connecting sub-graph of Vnembedded in G.
Now, let G0n:= (Vn0, En0 ∪ E0i∪ Eo0)be sub-graph of n in the other abstraction composed of a set of nodes Vn0, with internal En0 ⊆ Vn0×Vn0, in-going Ei0 ⊆ I ×Vn0and outgoing Eo0 ⊆ Vn0×O edges. The swapping from one abstraction to another is performed by substitution of the corresponding sub-graphs Gnand G0n in the original netlist G, to generate the substitute graph G0= (V0, E0)where V0:= {V \ Vn} ∪ Vn0 and E0 := {E \ En} ∪ E0n.
8.2.3 Mixed-abstraction Temporal Behavior
In mixed-level simulation of the circuit, all nodes are evaluated by the waveform pro- cessing algorithm of their respective abstraction which computes output waveforms in the corresponding abstractions. Therefore, waveforms of different abstractions can coexist
8.2 Multi-Level Circuit Modeling
during simulation. Each time a waveform encounters a node of a different abstraction, it crosses an ROI boundary. To allow the receiving node to process the waveform, the wave- form needs to be transformed to the abstraction of the node during the input processing. This work utilizes two transformations to map between high-level waveforms with discrete logic values and low-level waveforms with continuous voltages as presented in [SKW18]. These transformations map the events from logic- to switch and back from switch- to logic level accordingly.
Ternary Logic Waveforms
As mentioned earlier, switch level waveforms are continuous in value and for certain val- ues an undefined logic behavior is interpreted which can propagate through the circuit. The logic level waveforms are therefore extended to support ternary logic E3 = {0, 1, X} over a pseudo-Boolean algebra in order to model undefined values [Hay86].
For this, all events e ∈ w of a logic level waveform are distinguished between ordinary events and special events. With the exception of the initialization and sentinel event at t = −∞and t = ∞, all ordinary events e are considered to occur only at times 0 ≤ t < ∞. For the extension the special events e := (t) ∈ w are allowed negative event times t < 0. By consideration of the sign bit [IEE08] additional signal transition rules can be formulated for the waveforms. The sign of an event time t is accessed via the sign-function sgn : R → {0, 1}, where sgn(t) delivers 1, if the sign bit of the corresponding event time is set (t negative), or 0 otherwise (number is positive). The absolute value |t| of t ∈ e is considered as actual event time for temporal evaluation. Within each waveform all events are stored in temporal order according to their (absolute) event time |t|. Hence, for any two events ei, ej ∈ w with |ti| > |tj|, the respective indices in for the ordering are i > j.
In case sgn(t) = 1 holds for an event e = (t) with time t, e is declared a special event which triggers an irregular transition, that switches between undefined (’X’) and high (’1’) or low (’0’) values. All transitions between the different values are illustrated in the follow- ing state diagram of Fig. 8.1 from which the waveform function w is derived. Initially, each waveform has a low (’0’) initial value (init). For each following event ei with sgn(ti) = 0 the signal state then transitions in temporal order between high (’1’) and low (’0’). In case sgn(ti) = 1, the signal transitions to the unknown state (’X’) at time |ti|, which can be left
to either high or low depending on the next event in the order. Since the IEEE floating point standard [IEE08] distinguishes between −0 (sign-bit set) and 0 (sign-bit not set), transitions to unknown at time t = 0 are supported as well. For constant signals the corre- sponding waveform representations are w0 := {(∞)}for low, w1 := {(−∞), (−∞), (∞)} for high and wX := {(−∞), (∞)}for unknown values.
0 X 1 sgn(ti)=1 sgn(ti)=1 sgn(ti)=1 sgn(ti)=0 sgn(ti)=0 sgn(ti)=0 init
Figure 8.1: State transitions of events ei= (ti)in ternary E3 logic waveforms.
A more complex waveform using the ternary logic representation is illustrated in Fig. 8.2. As shown, the new waveform modeling can express all possible transitions in the three- valued E3 logic domain in a compact way. If no undefined values are present during sim- ulation, the processing of the waveforms is similar to the previous approach in [HSW12, HIW15] except for signal waveforms with an initial value of ’1’ for which an additional event at t = −∞ has to be stored.
0 X 1 0 1 2 3 4 5 6 7 Signal W time [a.u.] { (-∞), (-0.5), (-1), (1.5), (-2.5), (-3), (-4), (-4.5), (5.5), (6.5), (∞) }
Figure 8.2: Example of an arbitrary waveform over the ternary logic value domain E3.
8.2.4 Simulation Flow
The overall flow of the multi-level simulation approach combining both logic and switch level is shown in Fig. 8.3. After reading in the design (i.e., as netlist), the abstraction- independent combinational network of the netlist is extracted, topologically ordered and annotated with abstraction-dependent timing data (1). Once the circuit data is prepared, the user can define the regions of interest (ROI). The ROIs can be defined by specifying
8.2 Multi-Level Circuit Modeling
individual nodes for simulation with switch level accuracy (2), or by providing a fault set, where the individual fault locations provided are used as ROIs. Similar to faults, the defined ROIs can be grouped (3) for parallel simulation using the presented grouping heuristic (cf. Chapter 7).
fault set
combinational network extraction & levelization
netlist 1
define regions of interest 2 netlist & timing group regions 3 input stimuli reference responses transparent multi-level time simulation 5 output evaluation 6 switch level logic level output responses ROI groups mark current regions
4a
fault injection 4b
Figure 8.3: Overall flow-chart of the implemented multi-level fault simulation for com- bined logic- and switch level simulation. Shaded tasks are parallelized.
The ROI groups are then processed individually in subsequent simulation runs (step 4– 6). While processing a ROI, the simulator first marks all nodes of the current ROIs as active (4a). During this process, the timing descriptions of all activated ROI nodes are up- dated accordingly. Once the timing descriptions are set, the simulator is ready to perform the fault injection (4b), which allows for injection of logic level faults as well as transistor level parametric faults. The provided input stimuli set is then assigned to the circuit inputs and all nodes of the design are processed in topological order from inputs to outputs (5). Eventually, all output waveforms of the circuit have been computed and are ready for evaluation (6). In case of a fault simulation, reference responses provided via the response pattern memory are used to compute the output syndromes. After the evaluation, the ROI marks of all active nodes are cleared and the descriptions are restored.