3.1 Introduction to the chapter
3.5. Research Methods: Primary Data Gathering
3.5.3. Phase Two (Part B) Survey Survey
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY viterbimodif2 IS PORT( nA : IN std_logic_vector (21 DOWNTO 0); nA1 : IN std_logic_vector (21 DOWNTO 0); nA2 : IN std_logic_vector (21 DOWNTO 0); nA3 : IN std_logic_vector (21 DOWNTO 0); nA4 : IN std_logic_vector (21 DOWNTO 0); nA5 : IN std_logic_vector (21 DOWNTO 0); nA6 : IN std_logic_vector (21 DOWNTO 0); nA7 : IN std_logic_vector (21 DOWNTO 0); nA8 : IN std_logic_vector (21 DOWNTO 0); nB10 : IN std_logic_vector (21 DOWNTO 0); nB11 : IN std_logic_vector (21 DOWNTO 0); nB9 : IN std_logic_vector (21 DOWNTO 0); nP : IN std_logic_vector (21 DOWNTO 0); nP1 : IN std_logic_vector (21 DOWNTO 0); nP2 : IN std_logic_vector (21 DOWNTO 0); dout3 : OUT std_logic_vector (23 DOWNTO 0); dout4 : OUT std_logic_vector (23 DOWNTO 0); dout5 : OUT std_logic_vector (23 DOWNTO 0) ); -- Declarations
END viterbimodif2 ;
ARCHITECTURE struct OF viterbimodif2 IS -- Architecture declarations
-- Internal signal declarations SIGNAL corre : std_logic;
SIGNAL dbus0 : std_logic_vector(2 DOWNTO 0); SIGNAL dbus1 : std_logic_vector(2 DOWNTO 0);
SIGNAL dbus2 : std_logic_vector(2 DOWNTO 0); SIGNAL dout2 : std_logic_vector(21 DOWNTO 0); SIGNAL dout25 : std_logic_vector(21 DOWNTO 0); SIGNAL dout26 : std_logic;
SIGNAL dout27 : std_logic_vector(21 DOWNTO 0); SIGNAL dout28 : std_logic_vector(21 DOWNTO 0); SIGNAL prueba : std_logic;
SIGNAL puerto1 : std_logic_vector(1 DOWNTO 0); SIGNAL puerto2 : std_logic_vector(1 DOWNTO 0); SIGNAL puerto3 : std_logic_vector(1 DOWNTO 0); SIGNAL q : std_logic_vector(21 DOWNTO 0); SIGNAL q1 : std_logic_vector(21 DOWNTO 0); SIGNAL q10 : std_logic_vector(21 DOWNTO 0); SIGNAL q2 : std_logic_vector(21 DOWNTO 0); SIGNAL q3 : std_logic_vector(21 DOWNTO 0); SIGNAL q4 : std_logic_vector(21 DOWNTO 0); SIGNAL q5 : std_logic_vector(21 DOWNTO 0); SIGNAL q6 : std_logic_vector(21 DOWNTO 0); SIGNAL q7 : std_logic_vector(21 DOWNTO 0); SIGNAL q8 : std_logic_vector(21 DOWNTO 0); SIGNAL q9 : std_logic_vector(21 DOWNTO 0); SIGNAL shift : std_logic;
SIGNAL shift1 : std_logic; SIGNAL shift10 : std_logic; SIGNAL shift2 : std_logic; SIGNAL shift3 : std_logic; SIGNAL shift4 : std_logic; SIGNAL shift5 : std_logic; SIGNAL shift6 : std_logic; SIGNAL shift7 : std_logic; SIGNAL shift8 : std_logic; SIGNAL shift9 : std_logic; -- Component Declarations COMPONENT lnsmul PORT ( corre : IN std_logic; nA : IN std_logic_vector (19+2 DOWNTO 0); nB : IN std_logic_vector (19+2 DOWNTO 0); nR : OUT std_logic_vector (19+2 DOWNTO 0); shift : OUT std_logic );
END COMPONENT; COMPONENT selecx PORT (
puerto : IN std_logic_vector (2 DOWNTO 0); puerto1 : OUT std_logic_vector (1 DOWNTO 0) ); END COMPONENT;
-- Optional embedded configurations -- pragma synthesis_off
FOR ALL : lnsmul USE ENTITY lnsmul; FOR ALL : selecx USE ENTITY selecx; -- pragma synthesis_on
BEGIN
-- ModuleWare code(v1.7) for instance 'U_10' of 'comp' u_10combo_proc : PROCESS (q, q1)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q) >= unsigned(q1)) THEN temp_lout := '1';
END IF;
dbus0(2) <= temp_lout;
END PROCESS u_10combo_proc;
-- ModuleWare code(v1.7) for instance 'U_20' of 'comp' u_20combo_proc : PROCESS (q, q2)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q) >= unsigned(q2)) THEN temp_lout := '1';
END IF;
dbus0(1) <= temp_lout;
END PROCESS u_20combo_proc;
-- ModuleWare code(v1.7) for instance 'U_21' of 'comp' u_21combo_proc : PROCESS (q1, q2)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q1) >= unsigned(q2)) THEN temp_lout := '1';
END IF;
dbus0(0) <= temp_lout;
END PROCESS u_21combo_proc;
-- ModuleWare code(v1.7) for instance 'U_22' of 'comp' u_22combo_proc : PROCESS (q3, q4)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q3) >= unsigned(q4)) THEN temp_lout := '1';
END IF;
dbus1(2) <= temp_lout;
END PROCESS u_22combo_proc;
-- ModuleWare code(v1.7) for instance 'U_23' of 'comp' u_23combo_proc : PROCESS (q3, q5)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q3) >= unsigned(q5)) THEN temp_lout := '1';
END IF;
dbus1(1) <= temp_lout;
END PROCESS u_23combo_proc;
-- ModuleWare code(v1.7) for instance 'U_24' of 'comp' u_24combo_proc : PROCESS (q4, q5)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q4) >= unsigned(q5)) THEN temp_lout := '1';
END IF;
dbus1(0) <= temp_lout;
-- ModuleWare code(v1.7) for instance 'U_25' of 'comp' u_25combo_proc : PROCESS (q6, q7)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q6) >= unsigned(q7)) THEN temp_lout := '1';
END IF;
dbus2(2) <= temp_lout;
END PROCESS u_25combo_proc;
-- ModuleWare code(v1.7) for instance 'U_26' of 'comp' u_26combo_proc : PROCESS (q6, q8)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q6) >= unsigned(q8)) THEN temp_lout := '1';
END IF;
dbus2(1) <= temp_lout;
END PROCESS u_26combo_proc;
-- ModuleWare code(v1.7) for instance 'U_27' of 'comp' u_27combo_proc : PROCESS (q7, q8)
VARIABLE temp_lout : std_logic; BEGIN
temp_lout := '0';
IF (unsigned(q7) >= unsigned(q8)) THEN temp_lout := '1';
END IF;
dbus2(0) <= temp_lout;
END PROCESS u_27combo_proc;
-- ModuleWare code(v1.7) for instance 'U_29' of 'merge' dout3 <= puerto1 & dout25;
-- ModuleWare code(v1.7) for instance 'U_40' of 'merge' dout4 <= puerto2 & dout27;
-- ModuleWare code(v1.7) for instance 'U_41' of 'merge' dout5 <= puerto3 & dout28;
-- ModuleWare code(v1.7) for instance 'U_9' of 'mux' u_9combo_proc: PROCESS(q, q1, q2, puerto1) BEGIN
CASE puerto1 IS
WHEN "00"|"L0"|"0L"|"LL" => q9 <= q; WHEN "01"|"L1"|"0H"|"LH" => q9 <= q1; WHEN "10"|"H0"|"1L"|"HL" => q9 <= q2; WHEN OTHERS => q9 <= (OTHERS => 'X'); END CASE;
END PROCESS u_9combo_proc;
-- ModuleWare code(v1.7) for instance 'U_31' of 'mux' u_31combo_proc: PROCESS(q3, q4, q5, puerto2) BEGIN
CASE puerto2 IS
WHEN "00"|"L0"|"0L"|"LL" => q10 <= q3; WHEN "01"|"L1"|"0H"|"LH" => q10 <= q4; WHEN "10"|"H0"|"1L"|"HL" => q10 <= q5; WHEN OTHERS => q10 <= (OTHERS => 'X'); END CASE;
-- ModuleWare code(v1.7) for instance 'U_33' of 'mux' u_33combo_proc: PROCESS(q6, q7, q8, puerto3) BEGIN
CASE puerto3 IS
WHEN "00"|"L0"|"0L"|"LL" => dout2 <= q6; WHEN "01"|"L1"|"0H"|"LH" => dout2 <= q7; WHEN "10"|"H0"|"1L"|"HL" => dout2 <= q8; WHEN OTHERS => dout2 <= (OTHERS => 'X'); END CASE;
END PROCESS u_33combo_proc;
-- ModuleWare code(v1.7) for instance 'U_51' of 'xor'
corre <= shift XOR shift1 XOR shift2 XOR shift3 XOR prueba XOR shift4 XOR shift5 XOR shift6 XOR shift7;
-- ModuleWare code(v1.7) for instance 'U_86' of 'xor' dout26 <= shift8 XOR shift9 XOR shift10;
-- Instance port mappings. U_0 : lnsmul PORT MAP ( nA => nA, nB => nP, nR => q, corre => corre, shift => shift ); U_2 : lnsmul PORT MAP ( nA => nA1, nB => nP1, nR => q1, corre => corre, shift => shift1 ); U_3 : lnsmul PORT MAP ( nA => nA2, nB => nP2, nR => q2, corre => corre, shift => shift2 ); U_4 : lnsmul PORT MAP ( nA => nA3, nB => nP, nR => q3, corre => corre, shift => shift3 ); U_5 : lnsmul PORT MAP ( nA => nA4, nB => nP1, nR => q4, corre => corre, shift => prueba ); U_6 : lnsmul PORT MAP ( nA => nA5, nB => nP2, nR => q5,
corre => corre, shift => shift4 ); U_7 : lnsmul PORT MAP ( nA => nA6, nB => nP, nR => q6, corre => corre, shift => shift5 ); U_8 : lnsmul PORT MAP ( nA => nA7, nB => nP1, nR => q7, corre => corre, shift => shift6 ); U_34 : lnsmul PORT MAP ( nA => nA8, nB => nP2, nR => q8, corre => corre, shift => shift7 ); U_45 : lnsmul PORT MAP ( nA => q9, nB => nB10, nR => dout25, corre => dout26, shift => shift8 ); U_46 : lnsmul PORT MAP ( nA => q10, nB => nB11, nR => dout27, corre => dout26, shift => shift9 ); U_47 : lnsmul PORT MAP ( nA => dout2, nB => nB9, nR => dout28, corre => dout26, shift => shift10 ); U_28 : selecx PORT MAP ( puerto => dbus0, puerto1 => puerto1 ); U_30 : selecx PORT MAP ( puerto => dbus1, puerto1 => puerto2 ); U_32 : selecx PORT MAP ( puerto => dbus2, puerto1 => puerto3 );
END struct;
nR : (19+ 2:0 )
Loga rte s is 1 0 1 0 0 6 _ lib
q8 dbus 2(0 )
Loga rte s is 1 0 1 0 0 6 _ lib
S IGNA L q : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q1 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q2 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q3 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q4 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q5 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q6 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q7 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q8 : std_ logi c_ve ctor (21 DOWN TO 0 ) n P : std _log ic_v ecto r(21 DOW NTO 0) n P1 : std _log ic_v ecto r(21 DOW NTO 0) n P2 : std _log ic_v ecto r(21 DOW NTO 0) S IGNA L db us0 : std_ logi c_ve ctor (2 D OWNT O 0) S IGNA L pu erto 1 : std_ logi c_ve ctor (1 D OWNT O 0) S IGNA L db us1 : std_ logi c_ve ctor (2 D OWNT O 0) S IGNA L pu erto 2 : std_ logi c_ve ctor (1 D OWNT O 0) S IGNA L pu erto 3 : std_ logi c_ve ctor (1 D OWNT O 0) S IGNA L db us2 : std_ logi c_ve ctor (2 D OWNT O 0)
S IGNA L sh ift : std_ logi c S IGNA L sh ift1 : std_ logi c S IGNA L sh ift2 : std_ logi c S IGNA L sh ift3 : std_ logi c S IGNA L sh ift4 : std_ logi c S IGNA L sh ift5 : std_ logi c S IGNA L sh ift6 : std_ logi c S IGNA L sh ift7 : std_ logi c S IGNA L sh ift8 : std_ logi c S IGNA L sh ift9 : std_ logi c S IGNA L sh ift1 0 : std_ logi c n A : std _log ic_v ecto r(21 DOW NTO 0) n A1 : std _log ic_v ecto r(21 DOW NTO 0) n A2 : std _log ic_v ecto r(21 DOW NTO 0) n A3 : std _log ic_v ecto r(21 DOW NTO 0) n A4 : std _log ic_v ecto r(21 DOW NTO 0) n A5 : std _log ic_v ecto r(21 DOW NTO 0) n A6 : std _log ic_v ecto r(21 DOW NTO 0) n A7 : std _log ic_v ecto r(21 DOW NTO 0) n A8 : std _log ic_v ecto r(21 DOW NTO 0)
S IGNA L do ut2 : std_ logi c_ve ctor (21 DOWN TO 0 )
S IGNA L q9 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L q1 0 : std_ logi c_ve ctor (21 DOWN TO 0 ) n B9 : std _log ic_v ecto r(21 DOW NTO 0) n B10 : std _log ic_v ecto r(21 DOW NTO 0) n B11 : std _log ic_v ecto r(21 DOW NTO 0) d out3 : std _log ic_v ecto r(23 DOW NTO 0) d out4 : std _log ic_v ecto r(23 DOW NTO 0) d out5 : std _log ic_v ecto r(23 DOW NTO 0) S IGNA L do ut25 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L do ut27 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L do ut28 : std_ logi c_ve ctor (21 DOWN TO 0 ) S IGNA L pr ueba : std_ logi c S IGNA L do ut26 : std_ logi c S IGNA L co rre : std_ logi c
q 3 n P1
Loga rte s is 1 0 1 0 0 6 _ lib q 2 n P nP1 nA n A1 nA2
Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 2 n A : (1 9+2:0) n B : (1 9+2:0) nR : (19+ 2:0) sh ift c orre n A : (1 9+2:0) nR : (19+ 2:0) Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 0 nA : (19+ 2:0) nB : (19+ 2:0)sh ift c orre q q 1 c orre sh if t sh if t1 0 d bus 0 : (2:0) c om p U_10 0 1 0? 1 Un s ig ned q db us 0(2)
pu erto : (2:0)puerto1 : (1:0) p uerto 1 : (1 :0) pu erto1 0 c om p U_20 1 0? 1 Un s ig ned q1 db us 0(1) m u x q2 Loga rte s is 1 0 1 0 0 6 _ lib s e le c x U_ 2 8 Lo q q1 q9 nA : (19+2 :0 ) nR : (19+2 :0 ) nB10 m u x U_9 Hi nB : (19+2 :0 )shift c orre q 3 nP2 nA3
Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 3 n B : (1 9+2:0)shift c orre n A : (1 9+2:0) nR : (19+ 2:0) c orre sh if t2 x or U_51 nA4 Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 4 n B : (1 9+2:0) sh ift c orre n A : (1 9+2:0) nR : (19+ 2:0) sh if t q 4 n P c orre c o rre sh ift3 LIBRARY i eee; USE iee e.s td _l ogi c _11 64.al l; USE iee e.s td _l ogi c _ari th .al l ; pue rto : (2:0 ) dbus 0(0 ) c om p U_2 1 1 0? 1 Uns ig ned q 2 Pa c k a ge Lis t De c la ra tions Ports : lns m ul U_ 4 5shift8 c om p U_22 0 1 0? 1 Un s ig ned dbu s 1 : (2:0 ) dbu s 1(2 )
Dia gra m Signa ls : puerto1 : (1:0) x or U_8 6 p uerto 2 : (1 :0 ) p uerto 2 m erge U_ 29 m s b l s b dou t3 n B : (1 9+2:0)sh ift 0? 1 n P db us 2(2) nA5 nA6 Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 5 n B : (1 9+2:0) c orre
Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 6 n A : (1 9+2:0) n B : (1 9+2:0) nR : (19+ 2:0) sh if t c orre n A : (1 9+2:0) nR : (19+ 2:0) q 5 n P2 c orre c orre s hif t4 pr ueb a 0 U_31 sh ift dbus 1(0) c om p U_23 0 1 0? 1 Un s ig ned q 4 dbus 1(1) s e le c x U_ 3 0 m u x Lo Hi m ux nA : (19+2 :0) nR : (19+2 :0) q 3 q 4 q 5 sh ift9 q10 c om p U_24 1 0? 1 Un s ig ned 0 q 5 q6 nB1 1
Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 4 6 nB : (19+2 :0) c orre do ut2 6 n A7 nA8 Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 7 c orre
Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 8 n A : (1 9+2:0) n B : (1 9+2:0) nR : (19+ 2:0) sh if t c orre n A : (1 9+2:0) nR : (19+ 2:0) q 7 n P1 c orre c orre sh ift5 sh ift6 0 0? 1 c om p U_25 1 Un s ig ned q 6 dbus 2 : (2 :0 ) db us 2(1) Loga rte s is 1 0 1 0 0 6 _ lib s e le c x U_ 3 2 pue rto : (2:0)pue rto1 : (1:0)
p uerto 3 : (1 :0)pu erto3 c om p U_26 1 Un s ig ned 0 q7 m u x U_33 Lo Him u x nA : (19 +2:0) nB : (19 +2:0) nR : (19 +2:0) sh ift c o rre q6 q7 q8 do ut2 6 sh ift1 0 m erge U_4 1 m s b l s b m erge U_ 40 m s b l s b do ut5 d out4 by J o rge Alv a ra do on 02 Di c 2006 Pro jec t: <en te r di agram ti tl e here> Titl e: < enter c om m ents h ere>
Loga rtes i s 1 0100 6
<c om p any nam e >
Path: Edi te d:
Log artes is 1010 06_l i b/v iterbi m odi f2 /s truc t
Loga rte s is 1 0 1 0 0 6 _ lib lns m ul U_ 3 4 n B : (1 9+2:0)sh ift c orre c om p U_2 7 1 0? 1 Uns ig ned n B9 lns m ul U_ 4 7 q8 n P2 s hift7
Figura A.4 Esquemático de la unidad de Recursión.
A.6.3.1 Código de la unidad de banderas
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;
ENTITY selecx IS PORT(
puerto : IN std_logic_vector (2 DOWNTO 0); puerto1 : OUT std_logic_vector (1 DOWNTO 0) ); END selecx ; ARCHITECTURE tbl OF selecx IS -- Architecture declarations BEGIN --- truth_process_proc: PROCESS(puerto) --- BEGIN -- Block 1 IF (puerto = "000") THEN puerto1 <= "10";
ELSIF (puerto = "001") THEN puerto1 <= "01";
ELSIF (puerto = "010") THEN puerto1 <= "00";
ELSIF (puerto = "011") THEN puerto1 <= "01";
ELSIF (puerto = "100") THEN puerto1 <= "10";
puerto1 <= "00";
ELSIF (puerto = "110") THEN puerto1 <= "00";
ELSIF (puerto = "111") THEN puerto1 <= "00";
END IF;
END PROCESS truth_process_proc; -- Architecture concurrent statements END tbl;