System Generator for DSP

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System

Generator for

DSP

Getting Started Guide

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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.

THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.

© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

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Preface: About This Guide

Guide Contents

. . . 7

System Generator PDF Doc Set

. . . 7

Additional Resources

. . . 8

Conventions

. . . 8

Typographical . . . 8

Online Document . . . 9

Chapter 1: Introduction

The Xilinx DSP Block Set

. . . 12

FIR Filter Generation

. . . 13

Support for MATLAB

. . . 14

System Resource Estimation

. . . 15

Hardware Co-Simulation

. . . 16

System Integration Platform

. . . 17

Chapter 2: Installation

Downloading

. . . 19

Hardware Co-Simulation Support . . . 19

System Requirements and Recommendations

. . . 19

Hardware Recommendations . . . 19

Operating System and Software Requirements. . . 20

Compatibility with Other Tools . . . 20

Software Prerequisites . . . 21

Using the ISE Design Suite Installer

. . . 21

Installing System Generator On the Linux OS

. . . 21

Post Installation Tasks

. . . 29

Hardware Co-Simulation Installation . . . 29

Compiling Xilinx HDL Libraries . . . 29

Configuring the System Generator Cache . . . 30

Displaying and Changing Versions of System Generator . . . 30

Chapter 3: Release Information

Release Notes 11.4

. . . 33

System Generator Enhancements . . . 33

Xilinx Blockset Enhancements . . . 33

System Requirements and Recommendations . . . 35

Known Issues . . . 36

Release Notes 11.3

. . . 37

Release Notes 11.2

. . . 41

Release Notes 11.1

. . . 46

Xilinx Basic Building Block Enhancements . . . 49

Xilinx Blocks Superseded . . . 50

Release Notes 10.1.3

. . . 53

Xilinx DSP Blockset Enhancements . . . 53

Tool Flow and Integration . . . 54

Release Notes 10.1.2

. . . 55

Release Notes 10.1.1

. . . 57

Release Notes 10.1

. . . 59

Upgrading a Xilinx System Generator Model

. . . 61

Upgrading v2.x and Prior Models . . . 61

Upgrading v3.x, v6.x and v7.x Models . . . 61

Examples . . . 62

Chapter 4: Getting Started

Introduction

. . . 63

Lesson 1 - Design Creation Basics

. . . 64

The System Generator Design Flow . . . 64

The Xilinx DSP Blockset . . . 65

Defining the FPGA Boundary . . . 66

Adding the System Generator Token . . . 67

Creating the DSP Design . . . 68

Generating the HDL Code . . . 69

Model-Based Design using System Generator . . . 70

Creating Input Vectors using MATLAB . . . 71

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Lab Exercise: Getting Started with System Generator . . . 72

Lesson 2 - Fixed Point and Bit Operations

. . . 73

Fixed-Point Numeric Precision . . . 73

System Generator Fixed-Point Quantization . . . 74

Overflow and Round Modes . . . 75

Bit-Level Operations . . . 76

The Reinterpret Block . . . 77

The Convert Block . . . 78

The Concat Block . . . 79

Slice Block . . . 80

The BitBasher Block . . . 81

Lesson 2 Summary . . . 82

Lab Exercise: Signal Routing . . . 82

Lesson 3 - System Control

. . . 83

Controlling a DSP System . . . 83

The MCode Block . . . 84

The Xilinx “xl_state” Data Type . . . 85

State Machine Example . . . 86

The Expression Block . . . 87

Reset and Enable Ports . . . 88

Bursty Data . . . 89

Lesson 3 Summary . . . 90

Lab Exercise: System Control . . . 90

Lesson 4 - Multi-Rate Systems

. . . 91

Creating Multi-Rate Systems . . . 91

Up and Down Sampling Blocks . . . 92

Rate Changing Functional Blocks . . . 93

Viewing Rate Changes in Simulink . . . 94

Debugging Tools . . . 95

Sample Period “Rules” . . . 96

Lab Exercise: Multi-Rate Systems . . . 97

Lesson 5 - Using Memories

. . . 98

Block vs. Distributed RAM . . . 98

Initializing RAMs and ROMs . . . 99

System Generator RAM Blocks . . . 100

System Generator ROM Blocks . . . 101

The Delay Block . . . 102

The FIFO Block . . . 103

Shared Memory Block . . . 104

Lab Exercise: Using Memories . . . 105

Lesson 6 - Designing Filters

. . . 106

Introduction . . . 106

The Virtex DSP48 Math Slice . . . 107

FIR Compiler Block . . . 108

Creating Coefficients with FDATool . . . 109

Using FDA Tool Coefficients . . . 110

Lab Exercise: Designing Filters . . . 111

Additional Examples and Tutorials

. . . 112

Black Box Examples . . . 112

ChipScope Examples . . . 112

DSP Examples . . . 113

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Processor Examples . . . 114

Shared Memory Examples . . . 115

Timing Analysis Examples . . . 116

Miscellaneous Examples . . . 116

System Generator Demos . . . 117

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Preface

About This Guide

This Getting Started Guide introduces you to System Generator for DSP, then provides installation and configuration instructions, release information, and six mini-training modules that highlight the main features of the product. Each module starts with a lesson of 8-10 slides that explain important concepts, followed by a lab exercise that take about 30 minutes to complete. Because this introductory training is part of the tool, you can progress through the material at your own pace and on your own time schedule

Guide Contents

This Getting Started Guide contains the following topics: • Introduction

• Installation

• Release Information • Getting Started

a. Design Creation Basics

b. Fixed Point and Bit Operations c. System Control

d. Multi-Rate Systems e. Using Memories f. Designing Filters

g. Additional Examples and Tutorials

System Generator PDF Doc Set

This Getting Started Guide can be found in the System Generator Help system and is also part of the System Generator Doc Set that is provided in PDF format. The content of the doc set is as follows:

• System Generator for DSP Getting Started Guide

• System Generator for DSP User Guide

• System Generator for DSP Reference Guide

Note: Hyperlinks across these PDF documents work only when the PDF files reside in the same folder. After clicking a Hyperlink in the Adobe Reader, you can return to the previous page by pressing the Alt key and the left arrow key (←) at the same time.

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Preface: About This Guide

Additional Resources

To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm.

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support/mysupport.htm.

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier font Messages, prompts, and

program files that the system displays

speed grade: - 100

Courier bold _{Literal commands that you} enter in a syntactical statement

ngdbuild _{design_name}

Helvetica bold Commands that you select from a menu

File → Open Keyboard shortcuts Ctrl+C Italic font Variables in a syntax statement

for which you must supply values

ngdbuild design_name

References to other manuals See the Development System Reference Guide for more information.

Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. Square brackets [ ] An optional entry or parameter.

However, in bus specifications, such as bus[7:0]_{, they are} required.

ngdbuild [option_name]

design_name

Braces { } A list of items from which you must choose one or more

lowpwr ={on|off}

Vertical bar | Separates items in a list of choices

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Conventions

Online Document

The following conventions are used in this document: Vertical ellipsis

. . .

Repetitive material that has been omitted

IOB #1: Name = QOUT’ IOB #2: Name = CLKIN’

. . . Horizontal ellipsis . . . Repetitive material that has

been omitted

allow block _{block_name loc1}

loc2 ... locn;

Convention Meaning or Use Example

Blue text Cross-reference link to a location in the current document

See the topic “Additional Resources” for details. Refer to “Title Formats” in Chapter 1 for details. Red text Cross-reference link to a

location in another document

See Figure 2-5 in the Virtex-II Platform FPGA User Guide.

Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.

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Chapter 1 Introduction

System Generator is a DSP design tool from Xilinx that enables the use of the MathWorks model-based Simulink design environment for FPGA design. Previous experience with Xilinx FPGAs or RTL design methodologies are not required when using System Generator. Designs are captured in the DSP friendly Simulink modeling environment using a Xilinx specific blockset. All of the downstream FPGA implementation steps including synthesis and place and route are automatically performed to generate an FPGA programming file.

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Chapter 1: Introduction

The Xilinx DSP Block Set

Over 90 DSP building blocks are provided in the Xilinx DSP blockset for Simulink. These blocks include the common DSP building blocks such as adders, multipliers and registers. Also included are a set of complex DSP building blocks such as forward error correction blocks, FFTs, filters and memories. These blocks leverage the Xilinx IP core generators to deliver optimized results for the selected device.

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FIR Filter Generation

FIR Filter Generation

System Generator includes a FIR Compiler block that targets the dedicated DSP48 hardware resources in the Virtex®-4 and Virtex-5 devices to create highly optimized implementations that can run in excess of 500 Mhz. Configuration options allow generation of direct, polyphase decimation, polyphase interpolation and oversampled implementations. Standard MATLAB functions such as fir2 or the MathWorks FDAtool can be used to create coefficients for the Xilinx FIR Compiler.

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Support for MATLAB

Algorithmic MATLAB models can be incorporated into System Generator through AccelDSP™. AccelDSP includes powerful algorithmic synthesis that takes floating-point MATLAB as input and generates a fully scheduled fixed-point model for use with System Generator. Features include floating- to fixed-point conversion, Automatic IP insertion, design exploration and algorithmic scheduling. Also included in System Generator is an MCode block that allows the use of non-algorithmic MATLAB for the modeling and implementation of simple control operations.

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System Resource Estimation

System Resource Estimation

System Generator provides a Resource Estimator block that quickly estimates the area of a design prior to place and route. This can be a valuable aid in the hardware / software partitioning process by helping system designers take full advantage of the FPGA resources which include up to 640 multiply/accumulate (or DSP) blocks in the Virtex®-5 devices.

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Hardware Co-Simulation

System Generator provides accelerated simulation through hardware co-simulation. System Generator will automatically create a hardware simulation token for a design captured in the Xilinx DSP blockset that will run on one of over 20 supported hardware platforms. This hardware will co-simulate with the rest of the Simulink system to provide up to a 1000x simulation performance increase.

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System Integration Platform

System Integration Platform

System Generator provides a system integration platform for the design of DSP FPGAs that allows the RTL, Simulink, MATLAB and C/C++ components of a DSP system to come together in a single simulation and implementation environment. System Generator supports a black box block that allows RTL to be imported into Simulink and co-simulated with either ModelSim or Xilinx® ISE® Simulator. System Generator also supports the inclusion of a MicroBlaze™ embedded processor running C/C++ programs.

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Chapter 2 Installation

Downloading

System Generator is part of the ISE® Design Suite and may be download from the Xilinx web page. You may purchase, register, and download the System Generator software from the site at:

http://www.xilinx.com/ise/optional_prod/system_generator.htm

Note: In special circumstances, System Generator can be delivered on a CD. Please contact your Xilinx distributor if your circumstances prohibit you from downloading the software via the web.

Hardware Co-Simulation Support

If you have an FPGA development board, you may be able to take advantage of System Generator’s ability to use FPGA hardware co-simulation with Simulink simulations. The System Generator software includes support for the XtremeDSP Development Kit, the MicroBlaze™ Multimedia Demonstration boards, the MVI hardware platform, the ML402 Virtex®-4 platform, the ML506 Virtex-5 platform, and the Spartan-3A DSP 1800 starter platform and 3400 development platform. Additional System Generator board support packages provide support for additional hardware co-simulation platforms. System Generator board support packages can be downloaded from the following URL: http://www.xilinx.com/technology/dsp/thirdparty_devboards.htm

System Requirements and Recommendations

Hardware Recommendations

Table 2-1: Windows-Based Hardware Recommendations

Recommendation Notes

2.00 GB of RAM

600 MB of hard disk space Minimum Requirement

Xilinx® Hardware Co-Simulation Platform Required for the Hardware Co-Simulation Flow

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Chapter 2: Installation

Operating System and Software Requirements

Compatibility with Other Tools

System Generator is designed to work with other software tools in an integrated flow. System Generator is currently compatible with the following tools:

Table 2-2: Linux-Based Hardware Recommendations

4 GB of RAM

Table 2-3: Windows-Based Operating System and Software Requirements

Requirement Notes

Windows XP 32 bit Operating System SP2 (English Only)

Xilinx® ISE Design Suite Release 11.1 MathWorks MATLAB®, Simulink with Fixed-Point Toolbox Version 2008a or 2008b

MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2008b) Fixed-Point Toolbox required for signals greater than 53 bits

Table 2-4: Linux-Based Operating System and Software Requirements

Requirement Notes

Red Hat Linux 4u7, 32 and 64 bit Operating System (English Only)

Xilinx® ISE Design Suite Release 11.1 MathWorks MATLAB®, Simulink with Fixed-Point Toolbox Version 2008a and 2008b

MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2008b) Fixed-Point Toolbox required for signals greater than 53 bits

Table 2-5: Compatibility with Other Tools

Tool Version

Mentor Graphics ModelSim® SE and PE 6.4b

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Using the ISE Design Suite Installer

Software Prerequisites

Some features in System Generator require the following software to be installed:

• A logic synthesis tool. System Generator is fully compatible with Xilinx XST (included in the ISE Foundation bundle) and Synplify Pro v8.9 from Synopsys, Inc.

• A hardware description language (HDL) simulator is required only for co-simulating HDL modules within Simulink using System Generator. System Generator HDL co-simulation interfaces are compatible with the Xilinx® ISE® Simulator, and ModelSim SE from Model Technology Inc.

Note: The Microsoft Windows environment variable %XILINX% must be set and point to your ISE software installation directory.

ISE software service packs may be downloaded from the Xilinx Download Center: http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

Using the ISE Design Suite Installer

Before invoking the ISE® Design Suite Installer, it is a good idea to make sure that all instances of MATLAB are closed. When all instances of MATLAB are closed, launch the installer and follow the directions on the screen.

Choosing the MATLAB Version for a Windows OS Installation

As the last step of the System Generator Windows installation, click the check box of the MATLAB installation you wish to associate with this verison of System Generator, then click Apply.

If you don’t see a valid version of MATLAB listed, for example a version installed on a network device, click the Add Version button, browse to the MATLAB root directory of the unlisted version, then click Add. If you wish to associate this version of MATLAB with System Generator, click the check box of the newly listed MATLAB installation, then click Apply.

If you have no version of MATLAB available, click Choose Later to continue with the installation. At a later time, after you have installed MATLAB, you can associate that version of MATLAB with System Generator by executing the Windows menu item Start > All Programs > Xilinx ISE Design Suite 11.1 > DSP Tools > Select MATLAB version for Xilinx System Generator or by executing the sg_config command that is located in the bin directory of the sysgen tree that is installed on a Linux machine.

Installing System Generator On the Linux OS

1. Run xsetup under a 32-bit or 64-bit Linux machine. At the prompt type: ./xsetup and follow installation instructions as follows.

Note: The DSP Tools installer will ONLY install the code matching the determined OS type. - 32-bit Windows machines will only receive a win32 installation.

- 32-bit Linux machines will only receive a lin32 installation. - 64-bit Linux machines will only receive a lin64 installation.

The installation process for Linux will be shorter (fewer files delivered) than the Windows installer.

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a. Click Next > to start the installation proces

b. For the next two screens, accept the Software License and click Next > c. Select the Destination Directory for the ISE Design Tools and DSP Tools.

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Installing System Generator On the Linux OS

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Note: The Environment Setting screen should allow you to set the LD_LIBRARY_PATH for System Generator libraries and ISE libraries ONLY. Other Xilinx tools may append their library paths to the LD_LIBRARY_PATH at a later time.

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- The Installation Options screen will not show the capability to NOT run the post installation script. This is on by default.

- It will not launch the Matlab Configuration GUI. This is disabled during the installation for Linux only.

- It will make a script called sysgen_startup.m and place it into the $XILINX_DSP/sysgen/util directory. This script associates System

Generator dynamically into a Matlab session without modifying the Matlab installation.

f. Examine all the setting options in the Option Summary screen and click Install when you are ready

Note: You should get a dialog box for a “Successful completion of post installation.” as well as the “installation complete” dialog box.

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g. If you select Acquire or manage License Key option from above, the Xilinx License Configuration Manager dialog box will pop-up. Configure your license and click OK.

Note: You now should see the “Install has complete” dialog box.

2. The following directory/file should exist under the DSP_Tools installation directory when installed under Linux. This will not show here under windows.

<install_dir>/DSP_Tools/<OS>/install_logfiles/postinstall_<OS>.log <install_dir>/DSP_Tools/<OS>/sysgen/util/sysgen_startup.m

<install_dir>/DSP_Tools/<OS>/common/bin/sysgen

3. Make sure you include XILINXD_LICENSE_FILE, MATLAB and any other third party tools to the $PATH variables by modifying the “settings32.csh and settings32.sh” (on 32-bit Linux machines) or “settings64.csh and settings64.sh” (on 64-bit Linux machines) shell scripts generated by System Generator during the post-installation which can be found at <install_dir>/11.1/DSP_Tools.

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For settings32.csh or settings64.sh

There are two levels of settings32[64].csh and settings32[64].sh shell scripts generated by the unified installer – a common script and individual script for each application. The install locations may be different for different users but the directory structure defaults to something like this:

<install_dir>/Xilinx/11.1/ISE <install_dir>/Xilinx/11.1/DSP_Tools

This is where the scripts are located. The common script is located in:

<install_dir>/Xilinx/11.1

Source the settings32[64].csh[sh] file from the common area at location:

<install_dir>/Xilinx/11.1

by type the following at the shell command line: source settings32[64].csh[sh]

Note: This script will source all Xilinx Tools you choose to install during the unified installation

4. At a Linux terminal window prompt, type which sysgen to make sure that System Generator is included in the $PATH variable correctly. It should show the following path:

< install_dir >/Xilinx/11.1/DSP_Tools/<OS>/common/bin/sysgen

5. You are now ready to launch System Generator by typing: sysgen

Note: This will invoke MATLAB and dynamically add System Generator to that MATLAB session. At the top of the MATLAB Command Window, you should see the “Installed System Generator dynamically” messages. You are now ready to run System Generator.

The following are some expected messages under certain conditions. Four additional functions are provided to help you debug and retrieve status from the installation. a. If System Generator is already installed when this script runs, you will see the

following error message:

System Generator currently found installed into matlab default path.

b. The following four functions are used to find, verify, read and test the XML file in question.

xl_get_matlab_support_xmlfile

This MATLAB function will retrieve the expected location of the common XML file used for determining MATLAB support within System Generator.

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xl_verify_matlab_support_xmlfile

This matlab function will verify that the XML file exists and is readable. If no XML file exists, the following error message is thrown to the MATLAB console”

Could not find ml_supported.xml to determine supported versions of MATLAB with System Generator.

If the XML file is unreadable, the error message that is thrown to the MATLAB console is:

Could not read ml_supported.xml to determine supported versions of MATLAB with System Generator

xl_read_matlab_support_xmlfile

This MATLAB function reads and parses the XML file looking for the supported MATLAB version information and provides error/warning messages used by the

sysgen_startup.m script.

xl_test_matlab_support_xmlfile

This MATLAB function tests the current instantiated MATLAB session and compares its version to those which are supported. Errors or warnings will be displayed based on results of this comparison. If the XML file is devoid of information, the error thrown to the MATLAB console is as folows:

Matlab support table used by System Generator is empty!

If the XML file information does not conform to the expected format, the following error is thrown to the MATLAB console:

Input matlab support table is not well formed. It should have only 2 columns!

If you are using a version of MATLAB that is too old (unsupported), then you will see the following error messages:

System Generator will not properly function under this version of MATLAB!

Error occurred while attempting to install System Generator into MATLAB path.

If you are using a version of MATLAB that is too new, then you will see the following warning messages:

System Generator may not properly function under this version of MATLAB!

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Post Installation Tasks

Post Installation Tasks

Hardware Co-Simulation Installation

This topic provides links to hardware and software installation procedures for hardware co-simulation. If you do not plan to use hardware co-simulation, you may skip this topic.

Ethernet-Based Hardware Co-Simulation

Installing an ML402 Platform for Ethernet Hardware Co-Simulation Installing an ML506 Platform for Ethernet Hardware Co-Simulation Installing an ML605 Platform for Ethernet Hardware Co-Simulation

Installing a Spartan-3A DSP 1800A Starter Platform for Ethernet Hardware Co-Simulation Installing a Spartan-3A DSP 3400A Development Platform for Ethernet Hardware Co-Simulation

Note: If installation instructions for your particular platform are not provided here, please refer to the installation instuctions that come with your Platform Kit.

Installing the Proxy Executable for Linux Users

Running hardware co-simulation on a Linux machine requires that you first run a shell script that installs a proxy executable. Do the following:

1. Log into the root account on your Linux machine

2. Go to the bin directory where System Generator is installed. For example,

cd $XILINX_DSP/sysgen/bin

3. Run the shell script called install_pcap_proxy.sh. For example, at the shell command line type:

./install_pcap_proxy.sh

JTAG-Based Hardware Co-Simulation

Installing an ML402 Board for JTAG Hardware Co-Simulation Installing an ML605 Board for JTAG Hardware Co-Simulation Installing an ML605 Board for JTAG Hardware Co-Simulation

Third-Party Hardware Co-Simulation

As part of the Xilinx XtremeDSP™ Initiative, Xilinx works with distributors and many OEMs to provide a variety of DSP prototyping and development platforms. Please refer to the following Xilinx web site page for more information on available platforms:

http://www.xilinx.com/technology/dsp/thirdparty_devboards.htm

Compiling Xilinx HDL Libraries

If you intend to simulate System Generator designs using ModelSim, you must compile your IP (cores) libraries. This topic describes the procedure.

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ModelSim SE

The Xilinx tool that compiles libraries for use in ModelSim SE is named compxlib. The following command can, for example, be used to compile all the VHDL and Verilog libraries with ModelSim SE:

compxlib –s mti_se –f all –l all

Complete instructions for running compxlib can be found in the ISE Software Manual titled “Synthesis and Simulation Design Guide”.

Configuring the System Generator Cache

Both the System Generator simulator and the design generator incorporate a disk cache to speed up the iterative design process. The cache does this by tagging and storing files related to simulation and generation, then recalling those files during subsequent simulation and generation rather than rerunning the time consuming tools used to create those files.

Setting the Size

By default, the cache will use up to 500 MB of disk space to store files. To specify the amount of disk space the cache should use, set the SYSGEN_CACHE_SIZE environment variable to the size of the cache in megabytes. Set this number to a higher value when working on several large designs.

Setting the Number of Entries

The cache entry database stores a fixed number of entries. The default is 20,000 entries. To set size of the cache entry database, set the SYSGEN_CACHE_ENTRIES environment variable to the desired number of entries. Setting this number too small will adversely affect cache performance. Set this number to a higher value when working on several large designs.

You can use the xlCache function to manage and inspect the properties of difference caches used by System Generator. A detailed description of this function can be found under the topic System Generator Utilities.

Displaying and Changing Versions of System Generator

It is possible to have several versions of System Generator installed. The MATLAB command xlVersion displays which versions are installed, and makes it possible to switch from one to another. xlVersion is useful when upgrading a model to run in the latest version of System Generator.

Entering "xlVersion" in the MATLAB console displays the versions of System Generator that are installed, and entering "xlVersion <version>" switches to the specified version. For example, if the versions that are installed are 9.2.01 and 11.1, and the currently selected version is 11.1, then entering "xlVersion" displays

Available System Generator installations:

Version 9.2.01 in C:/Xilinx/9.2.01/DSP_Tools/sysgen Version 11.1 in C:/Xilinx/11.1/DSP_Tools/sysgen Current version of System Generator is 11.1.

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Post Installation Tasks

Occasionally, it is necessary to restart MATLAB to make it possible to switch. In this case, the response to entering "xlVersion 11.1" looks like the following:

Please restart MATLAB and run xlVersion 11.1 again to switch.

When the switch succeeds, xlVersion prints the following:

Your System Generator has been switched. Please restart MATLAB.

If you install System Generator 11.1 after you install 9.2.01, you need to install 11.1 again in order to make xlVersion work.

Once you switch System Generator version, you need to switch to the right version of ISE in order to make System Generator work correctly.

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Chapter 3 Release Information

Release Notes 11.4

System Generator Enhancements

New Device Support

• Spartan®-6 Low Power • Spartan-6 XA

New Platform Support

System Generator now supports Ethernet HW co-simulation for the Virtex®-6 ML605 Platform

Xilinx Blockset Enhancements

New Blocks

DSP48 Macro 2.0

New block now available in System Generator with the following features: • The primary change is that the DSP48 Macro block is now supported by an

underlying LogiCORE rather than being a System Generator basic block.

• Expanded instruction functionality coverage with the addition of 77 new opcode instructions, bringing the opcode count from 72 to 149.

• Additional pipelining capability with the addition of Opmode, M Reg, and P Reg Stages. The Macro supports three latency modes (automatic, tiered and expert). Automatic and tiered are square latency models, the difference being that automatic gives a fully pipelined model where as tiered allows for finer control.

• Reset & Enable Ports: DSP Macro v2.0 provides a global sclr (rst in System Generator) and ce (en in System Generator) and does not provide access to individual enable and reset ports of various registers in the XtremeDSP slice.

• Support for Pre-Adder in Virtex-6, Spartan-6 and Spartan-3A DSP families, including the Pre-Adder D Port.

• Support for various rounding capabilities.

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Chapter 3: Release Information

Existing Block Updates

The following blocks have been updated with the features mentioned below.

Complex Multiplier 3.1

• Support added for Spartan-6L and Spartan-6 XA • Option added to configure latency.

Note: This block supersedes the Complex Multiplier 3.0 block

Convolution Encoder 7.0

• Support added for Virtex-6 and Spartan-6

• Support has been added for all features in the underlying LogiCORE including the puncturing feature.

Note: This block supersedes the Convolutional Encoder v6_1 block. The Convolution Encoder 7.0 block presents the same customization and port interface that is available in the underlying LogiCORE. The aclr input port has been removed.

Interleave Deinterleaver 5.1

• Support added for Spartan-3A DSP

Note: This block supersedes the Interleaver Deinterleaver v5_0 block. The Interleaver Deinterleaver 5.1 block presents the same customization and port interface that is available in the underlying LogiCORE.

Reed-Solomon Decoder 7.0

• Area optimization is now only selectable for the Virtex-5 family

• The maximum number of check symbols has been increased to 256 (was 128). Note: This block supersedes the Reed-Solomon Decoder 6.1 block. The Reed-Solomon Decoder 7.0 block presents the same customization and port interface that is available in the underlying LogiCORE. The aclr input port has been removed. The asynchronous reset input port (reset) has been removed.

Reed-Solomon Encoder 7.0

Note: This block supersedes the Reed-Solomon Decoder 6.1 block. The Reed-Solomon Decoder 7.0 block presents the same customization and port interface that is available in the underlying LogiCORE. The aclr input port has been removed. The asynchronous reset input port (reset) has been removed.

Viterbi Decoder 7.0

Note: This block supersedes the Viterbi Decoder v6_1 block. The Viterbi Decoder 7.0 block presents the same customization and port interface that is available in the underlying LogiCORE. The aclr input port and the speed option has been removed.

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Release Notes 11.4

System Requirements and Recommendations

Hardware Recommendations

Operating System and Software Requirements

2.00 GB of RAM

Table 3-1:

Windows-Based Requirements Notes Windows XP Professional 32-bit/64-bit

Operating System SP2 (English Only)

The 32-bit Windows edition of ISE® Design Suite 11 including System Generator for DSP is supported on the 64-bit operating system

Windows Vista Business 32-bit/64-bit Operating System (English Only)

The 32-bit Windows edition of ISE Design Suite 11 including System Generator for DSP is supported on the 64-bit operating system

Xilinx® ISE® Design Suite 11.4

MathWorks MATLAB® Version 2009a or 2009b MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2009a) Fixed-Point Toolbox required for signals greater than 53 bits

MathWorks Simulink with Fixed-Point Toolbox Version 2009a or 2009b

MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2009a) Fixed-Point Toolbox required for signals greater than 53 bits

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Known Issues

Known issues with System Generator can be found at the following Xilinx web site address:

http://www.xilinx.com/support/answers/29595.htm Table 3-2:

Linux-Based Requirements Notes

Red Hat Enterprise Linux WS v4.7, 32bit/64 -bit Operating System (English Only)

Red Hat Linux 5.2, 32-bit/64-bit Operating System (English Only)

SUSE Linux Enterprise v10.1, 32-bit/64-bit Operating System (English Only)

MathWorks MATLAB® Version 2009a or 2009b MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2009a) Fixed-Point Toolbox required for signals greater than 53 bits

MathWorks MATLAB®, Simulink with Fixed-Point Toolbox Version 2009a and 2009b

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Release Notes 11.3

System Generator Enhancements

New Device Support

• Virtex®-6 Lower Power (Virtex-6 -1L) • Virtex-6 HXT

• Virtex-5Q

New Platform Support

System Generator now supports JTAG HW co-simulation for the Spartan®-6 SP605 Platform

New Operating System Support

Full support for the following operating systems has been added: • Windows Vista Business 32-bit (English)

• Red Hat Enterprise Desktop 5.2, 32 & 64-bit • SUSE Linux Enterprise 10, 32 & 64-bit

Xilinx Blockset Enhancements

New Blocks

CIC Compiler 1.3

New block now available in System Generator with the following features: • Supports Virtex-6 and Spartan-6

• Input and output streaming interface added for multiple channel implementations. • Capability added to specify hardware over sampling specification as a sample period. • Capability added to leverage over sampling factor to optimize resource utilization. • nd (new data) input port is now only placed on the block when Sample Period is

selected as the format.

Note: This block supersedes the CIC Compiler 1.2 block. The RATE_WE signal no longer acts as a reset to the core, the core will update to the new rate on the next input sample, for a single channel implementation, or the next input to the first channel, for multiple channel implementations.

Refer to the topic CIC Compiler 1.3 for more information.

DDS Compiler 4.0

New block now available in System Generator with the following features:

• New option added to use the block as a Phase Generator or SIN/COS Lookup Table only. This capability allows users to custom build a Direct Digital Synthesizer to fit individual application needs.

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• Option to configure DDS using system-level parameters (SFDR and frequency resolution) or hardware parameters (phase and output width)

• Option to configure phase increment and phase offset as constant, programmable or dynamic (for modulation)

Note: This block supersedes the DDS Compiler 3.0 block. DDS Compiler 4.0 is not bit-accurate with respect to earlier versions. Also, there are latency changes of phase offset effects that have been balanced with the latency of phase increment for ease of use in the streaming modes. These latency changes also apply to existing programmable and fixed modes.

Refer to the topic DDS Compiler 4.0 for more information.

Existing Block Updates

• MULT, CMULT - now use the Multiplier LogiCORE v11.2 which leverages speed and area optimization for LUT implementation

• Upsample block - A new Latency parameter has been added which aids in timing closure by separating the fast and slow clock domains. The sample latency delay is added to the input of the Upsample block i.e. the slow clock domain

• The following blocks have been upgraded to support Virtex-6 Lower Power (i.e. no change in block functionality) and Virtex-5Q:

♦ ROM, Single Port Ram, Dual Port RAM, Shared Memory now use the Block Memory Generator v3.3 LogiCORE.

♦ ROM, Single Port Ram, Dual Port RAM now use the Distributed Memory Generator v4.2 LogiCORE

♦ FIFO, From FIFO ,ToFIFO now use the FIFO Generator v5.3 LogiCORE Refer to the topic Xilinx LogiCORE Versions for more information on other blocks that support Virtex-6 Lower Power and Virtex-5Q.

Discontinued System Generator Features

Support for FSL (Fast Simplex Link)

Starting with Release 11.3, further development of System Generator support for the FSL bus on the EDK Processor block has been discontinued. You may continue to use FSL with ISE® Design Suite 11, however, FSL support will not be included in ISE Design Suite 12.

System Requirements and Recommendations

Hardware Recommendations

2.00 GB of RAM

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Operating System and Software Requirements

Table 3-3:

Windows-Based Requirements Notes Windows XP Professional 32-bit/64-bit

Operating System SP2 (English Only)

The 32-bit Windows edition of ISE® Design Suite 11 including System Generator for DSP is supported on the 64-bit operating system

Windows Vista Business 32-bit/64-bit Operating System (English Only)

The 32-bit Windows edition of ISE Design Suite 11 including System Generator for DSP is supported on the 64-bit operating system

MathWorks MATLAB® Version 2008b or 2009a MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2009a) Fixed-Point Toolbox required for signals greater than 53 bits

MathWorks Simulink with Fixed-Point Toolbox Version 2008b or 2009a

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Known Issues

Red Hat Enterprise Linux WS v4.7, 32bit/64 -bit Operating System (English Only)

Red Hat Linux 5.2, 32-bit/64-bit Operating System (English Only)

SUSE Linux Enterprise v10.1, 32-bit/64-bit Operating System (English Only)

MathWorks MATLAB® Version 2008b or 2009a MATLAB must be installed in a directory with no spaces (e.g., C:\MATLAB\R2009a) Fixed-Point Toolbox required for signals greater than 53 bits

MathWorks MATLAB®, Simulink with Fixed-Point Toolbox Version 2008b and 2009a

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Release Notes 11.2

System Generator Enhancements

Comprehensive DSP Design Platform Support for Virtex

®

-6 and Spartan

®

-6

• Xilinx Block Set updates. Key updates are listed below:

♦ DSP48 Macro, ChipScope Pro, PicoBlase Microcontroller ♦ Shared Memory Blockset

♦ Refer to the topic Xilinx LogiCORE Versions for detailed information

♦ Complex Multiplier 3.0, FIR Compiler 5.0 and Fast Fourier Transform 7.0 leverage the XtremeDSP™ slice pre-adder

• Added JTAG-based Hardware Co-Simulation support for ML605 Virtex-6 FPGA Platform.

• Support for Synplify Pro version C2009.06

Hardware Co-Simulation Enhancements

• Support for Linux Point-to-Point Ethernet Hardware Co-Simulation

Support Added for the Following Defense-Grade Device Families

• QPro Virtex-4 Hi-Rel • QPro Virtex-4 Rad Tolerant

Support for MATLAB 2009a

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Xpower Integration with System Generator

XPower is now integrated into the Timing and Power Analysis flow and the Bitstream flow. This allows you to analyze the power consumption of your System Generator design without leaving the MATLAB and Simulink environment.

As shown above, you select the flow, click the button to the right of the dialog box and select the Power Analysis option.

The default is No analysis. Quick analysis is fast but provides less accuracy.

Full simulation-based analysis automatically invokes an HDL simulation run on the design using the Xilinx ISim simulator. This takes longer, but provides the most accurate analysis.

1. Select the Flow

3. Select Analysis Type 2. Click

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After the analysis is complete, the Timing Analyzer dialog box appears. When You click the Power Analysis button as shown below, the Xilinx XPower Analyzer tool is invoked with the power analysis results displayed.

Xilinx Blockset Enhancements

DDS Compiler 3.0

Note: This block supersedes the DDS Compiler 2.1 block. Refer to the topic DDS Compiler 3.0 for more information.

Divider Generator 3.0

Note: This block supersedes the Divider Generator 2.0 block. Refer to the topic Divider Generator 3.0 for more information. 1. Click

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Fast Fourier Transform 7.0

• Option added to automatically select the best implementation based on target clock frequency and data throughput

• Configurable input data timing (No offset or 3-cycle input delay)

• Option to implement complex multipliers using either LUTs, resource-optimized 3-multiplier XtremeDSP slice structure or performance-optimized 4-3-multiplier XtremeDSP slice structure

• Leverages the pre-adder in Virtex-6 and Spartan-6 XtremeDSP slice for complex multiplier implementation

Note: This block supersedes the Fast Fourier Transform 6.0 block. Refer to the topic Fast Fourier Transform 7.0 for more information.

FIR Compiler 5.0

• Leverages the pre-adder in the Virtex-6 and Spartan-6 XtremeDSP slice for symmetric filter implementation

• Extended clock and sample frequency range for Fixed Fractional Rate Decimation structure

• Option added to explicitly set hardware oversampling rate Note: This block supersedes the FIR Compiler 4.0 block.

Refer to the topic FIR Compiler 5.0 for more information.

System Requirements and Recommendations

Hardware Recommendations

2.00 GB of RAM

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Operating System and Software Requirements

Known Issues

Windows-Based Requirements Notes Windows XP 32 bit Operating System SP2

(English Only)

Xilinx® ISE Design Suite Release 11.1.2 MathWorks MATLAB® Version 2008b or 2009a MathWorks Simulink with Fixed-Point Toolbox Version 2008b or 2009a

Table 3-6:

Red Hat Linux 4.7, 32 and 64 bit Operating System (English Only)

Xilinx® ISE Design Suite Release 11.1.2 MathWorks MATLAB® Version 2008b or 2009a MathWorks MATLAB®, Simulink with Fixed-Point Toolbox Version 2008b and 2009a

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Release Notes 11.1

System Generator Enhancements

Linux Support

System Generator now supports the Red Hat Enterprise Linux 4 WS (32 and 64-bit) operating system. The topic Installing System Generator On the Linux OS provides detailed installation instructions that are specific to Linux.

New MATLAB 2008b Support

For this release, System Generator now supports MATLAB 2008b and MATLAB 2008a.

Using Platform Studio SDK with System Generator

The Xilinx Platform Studio Software Development Kit (SDK) is an Integrated

Development Environment for creating software platform designs. The SDK is an eclipse- based IDE that makes it easier to write high quality C/C++ code for Xilinx embedded processors. System Generator provides access to the SDK by automatically generating an SDK workspace and providing a "hello world" program template that contains example code which allows users to write productive code in a short period of time. For more details on how this feature works, refer to the topic titled Using Platform Studio SDK.

Updated Design Examples

For this release, the designs in the Examples folder have been updated. They use the latest IP and they target the latest devices.

Support for Bi-Directional Ports

The System Generator Black Box now supports HDL that contain "inout" top-level port declarations. These bi-directional ports will not be displayed in the Simulink diagram, but will be present in the generated System Generator HDL. The bi-directional ports can also be driven with data from a text file during a System Generator simulation. Refer to the topic titled Black Box Configuration M-Function for information on how to enable bi-directional ports.

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Viewing XReports from System Generator

Viewing XReports after Compilation

As shown below, when you compile a design with the target specified as Bitstream or Timing Analysis, the Compilation status dialog box now appears with a new Show Reports button. When you click on the Show Reports button, the associated XReports will be available for your viewing:

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Viewing XReports from the Estimator Block

If your design contains an Estimator block and you select the Post Map Estimate option, the Running Resource Estimator dialog box appears with a new Show Reports button (as shown below). You can then click on the Show Reports button and the associated XReports will be available for your viewing:

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Xilinx Blockset Enhancements

Complex Multiplier 3.0

New block now available in System Generator with the following features: • Multiplies two complex numbers

• All operands and the results are represented in signed two’s complement format • The operand widths and the result width are parameterizable

Refer to the topic Complex Multiplier 3.0 for more information.

CORDIC 4.0

New block now available in System Generator with the following features: • Implements a generalized coordinate rotational digital computer (CORDIC)

algorithm with the following equation types ♦ Rectangular <-> Polar conversion ♦ Trigonometric

♦ Hyperbolic ♦ Square root

• Provides two architectural configurations

♦ A fully parallel configuration with single-cycle data throughput at the expense of silicon area

♦ A word serial implementation with multiple-cycle throughput but occupying a small silicon area

• The CORDIC algorithm introduces a scale factor to the amplitude of the result • The CORDIC core provides an option to automatically compensate for the CORDIC

scale factor

Refer to the topic CORDIC 4.0 for more information.

EDK Processor Block Enhancements

• Initial Program file (.ELF file) can now be set. When a bitstream containing an EDK Processor is created using the Bitstream or Hardware Co-simulation compilation target, the initial program file pointed to in this field will be loaded into the program memory of the processor after the bitstream has been created.

♦ Register Read-Back: Typically interfaces on the memory-map are uni-directional; the registers can either be read-from or write-to from the processor. When Register Read-Back is enabled, From-Registers that can be written-to from the processor can also be read-from. Turning on this functionality will add more entries to the memory map and will incur a speed and area penalty.

Xilinx Basic Building Block Enhancements

The following basic building blocks have been updated and enhanced for this release: • Adder Subtractor 11.0

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• Multiplier 11.0

• RAM-Based Shift Register 11.0

• Updated memory blocks to use Block Memory Generator 3.1, Distributed Memory Generator 4.1 and FIFO Generator 5.1

♦ Single Port RAM ♦ Dual Port RAM

♦ ROM

♦ FIFO

♦ Shared Memory ♦ To FIFO

♦ From FIFO

Xilinx Blocks Superseded

The following Xilinx DSP Blocks have been superseded. The table below lists the recommended replacement block.

Table 3-7: Xilinx DSP Superseded Blocks

Superseded Block Replacement Block

CIC Compiler 1.0 CIC Compiler 1.2

CIC Compiler 1.1 CIC Compiler 1.2

Convolutional Encoder v3_0 Convolutional Encoder v6_1 Convolutional Encoder v6_0 Convolutional Encoder v6_1

DDS Compiler v1_1 DDS Compiler 2.1

DDS v4_0 DDS Compiler 2.1

DDS v5_0 DDS Compiler 2.1

FFT v1_0 Fast Fourier Transform 6.0

FIR Compiler v1_0 FIR Compiler 4.0

Interleaver Deinterleaver v4_0 Interleaver Deinterleaver v5_0

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System Requirements and Recommendations

Hardware Recommendations

Operating System and Software Requirements

RS Decoder v6_0 Read-Solomom Decoder 6.1

RS Eecoder v5_0 Read-Solomom Encoder 6.1

RS Eecoder v6_0 Read-Solomom Encoder 6.1

Viterbi Decoder v5_0 Viterbi Decoder v6_1 Viterbi Decoder v6_0 Viterbi Decoder v6_1 Table 3-7: Xilinx DSP Superseded Blocks

Superseded Block Replacement Block

2.00 GB of RAM

Table 3-8:

Windows-Based Requirements Notes Windows XP 32 bit Operating System SP2

(English Only)

Xilinx® ISE Design Suite Release 11.1

MathWorks MATLAB® Version 2008a or 2008b MathWorks Simulink with Fixed-Point Toolbox Version 2008a or 2008b

MATLAB must be installed in a directory with no spaces (e.g.,

C:\MATLAB\R2008b)

Fixed-Point Toolbox required for signals greater than 53 bits

Table 3-9:

Red Hat Linux 4u7, 32 and 64 bit Operating System (English Only)

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Known Issues

http://www.xilinx.com/support/answers/29595.htm MathWorks MATLAB® Version 2008a or 2008b

MathWorks MATLAB®, Simulink with Fixed-Point Toolbox Version 2008a and 2008b

MATLAB must be installed in a directory with no spaces (e.g.,

C:\MATLAB\R2008b)

Fixed-Point Toolbox required for signals greater than 53 bits

Table 3-9:

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Release Notes 10.1.3

Release Notes 10.1.3

Xilinx DSP Blockset Enhancements

DSP48 Abstraction for Mathematical Operators

Accumulator, AddSub, and Counter blocks can now be implemented using either a DSP48 or the original LUT-based implementation. This enables design portability across all supported Xilinx devices.

Fast Fourier Transform 6.0

New block now available in System Generator with the following features: • Extended data and phase factor width to 34 bits

• Block floating-point support available for Pipelined, Streaming I/O architecture

WaveScope

• WaveScope waveforms can now be directly sent to a printer from WaveScope and a “Print Preview” capability allows you to view and customize the waveform formatting before printing. The capability can be accessed via the File pull-down menu or a toolbar shortcut.

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Tool Flow and Integration

System Generator 10.1.3 is compatible with the following tools:

Known Issues

http://www.xilinx.com/support/answers/29595.htm

The MathWorks MATLAB® and Simulink 2007b and 2008a Mentor Graphics ModelSim® SE 6.3c

Synplicity Synplify Pro® 8.8.0.4 (Requires a floating license for Hardware Co-Simulation)

Xilinx® AccelDSP 10.1.03

Xilinx® ChipScope Pro 10.1.03

Xilinx® EDK 10.1.03

Xilinx® ISE 10.1.03

Xilinx® ISE IP Update 10.1 IP Update 3

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Release Notes 10.1.2

System Generator Enhancements

Hybrid DCM-CE Support

In the 10.1 release, System Generator introduced a new clocking option to automatically include a DCM (Digital Clock Manager) in a design. This option was limited to designs with no more than three clock rates.

In this release, this clocking option has been enhanced to support designs with more than three clock rates. The additional rates are automatically supported with the CE(Clock Enable) methodology. For example, if a design has six clock rates, the highest three clock rates are supported with a DCM and the lowest three clock rates are supported with the CE methodology.

MATLAB 2008a

MATLAB 2008a is now supported by System Generator.

Xilinx DSP Blockset Enhancements

FIR Compiler 4.0

New block now available in System Generator with the following features. • Extended data and coefficient width range up to 49 bits.

• Polyphase filter bank support for channelizer applications & transpose multiply-accumulate architecture.

• Capability to share control and coefficient memory resources for up to 16 parallel data paths.

• Virtex-5 and Spartan-3A DSP support added for distributed arithmetic architecture. This block supports all the features supported by FIR Compiler LogiCORE v4.0.

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Divider Generator 2.0

New block now available in System Generator that generates arithmetic division algorithms for integer division.

• Optional operand widths up to 54 bit wide, synchronous controls, and selectable latency.

• Supports Virtex-4, Virtex-5 & Spartan3A-DSP for both radix-2 integer division and high-radix division algorithms.

Tool Flow and Integration

Known Issues

The MathWorks MATLAB® and Simulink 2007b and 2008a Mentor Graphics ModelSim® SE 6.3c

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Release Notes 10.1.1

System Generator Enhancements

• Enhanced UCF Support for EDK Import Flow

The handling of UCF (User Constraint File) files in the EDK import flow has been enhanced to support larger UCF file sizes. The UCF file of an imported XPS project is now parsed and modified to form a new UCF file based on the settings of the EDK Processor block. The user has the ability to view and modify the original UCF file and then re-import the XPS project.

• Enhanced PLB Dual Clock Support

Xilinx Platform Studio projects that use clock generators to drive the PLB bus, MicroBlaze™ processor and other hardware peripherals with different clocks can now automatically be imported into System Generator for HDL netlisting and hardware co-simulation.

Xilinx DSP Blockset Enhancements

CIC Compiler 1.2

Update to existing block

• Simulation speedup of ~4x as compared to CIC Compiler 1.1

DDS Compiler 2.1

Update to existing block.

• Core generation time has been reduced by ~10x as compared to previous versions of the DDS Compiler.

• Ability to specify negative frequencies.

• In the previous version of the DDS Compiler, after reset has been de-asserted, the RDY output goes high 1-cycle too early; this error has been corrected.

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Tool Flow and Integration

Known Issues

The MathWorks MATLAB® and Simulink 2007a and 2007b Mentor Graphics ModelSim® SE 6.3c

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Release Notes 10.1

System Generator Enhancements

System Generator / Project Navigator Integration

System Generator designs can now be more easily incorporated into a larger design inside of Project Navigator by using a new source type in Project Navigator. The System Generator design can also be launched from Project Navigator.

DCM Support

System Generator now provides the option to automatically include a DCM in a design. Although the optional DCM is abstracted away from the designer, the generated design will leverage DCMs available in the silicon.

An alternative option exposes the clock ports at the top level for manual connection to a DCM.

Dual Asynchronous-Clock Support for PLB46

This capability gives the designer additional flexibility by allowing the DSP and embedded processing portions of a design to run at different clock rates.

Run Time Speed Improvements

• Up to 2x faster first time initialization of a simulation

• >10x faster initialization when loading the Xilinx Blockset in the Simulink Library Browser

M-Based HW Co-Simulation

System Generator models compiled for HW Co-Simulation can now be embedded, configured and utilized in a MATLAB M-code script; allowing for calls into hardware to be made from MATLAB.

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Xilinx DSP Blockset Enhancements

FFT 5.0

Update to existing block which now includes cyclic prefix insertion

FIR Compiler 3.2

Update which now include support for Virtex II and Spartan 3A.

Reset Generator

New block that produces synchronized downsampled reset signals which eliminates the need to manually create these signals.

CIC Compiler 1.1

New block now available in System Generator.

Tool Flow and Integration

System Generator 10.1 is compatible with the following tools:

Known Issues

The MathWorks MATLAB® and Simulink 2007a and 2007b Mentor Graphics ModelSim® SE 6.3c

Xilinx® AccelDSP 10.1

Xilinx® ChipScope Pro 10.1

Xilinx® EDK 10.1

Xilinx® ISE 10.1

System Generator for DSP

System

Generator for

DSP

Getting Started Guide

Preface: About This Guide

Guide Contents

System Generator PDF Doc Set

Additional Resources

Conventions

Chapter 1: Introduction

The Xilinx DSP Block Set

FIR Filter Generation

Support for MATLAB

System Resource Estimation

Hardware Co-Simulation

System Integration Platform

Chapter 2: Installation

Downloading

System Requirements and Recommendations

Using the ISE Design Suite Installer

Installing System Generator On the Linux OS

Post Installation Tasks

Chapter 3: Release Information

Release Notes 11.4

Release Notes 11.3

Table of Contents

Release Notes 11.2

Release Notes 11.1

Release Notes 10.1.3

Release Notes 10.1.2

Release Notes 10.1.1

Release Notes 10.1

Upgrading a Xilinx System Generator Model

Chapter 4: Getting Started

Introduction

Lesson 1 - Design Creation Basics

Lesson 2 - Fixed Point and Bit Operations

Lesson 3 - System Control

Lesson 4 - Multi-Rate Systems

Lesson 5 - Using Memories

Lesson 6 - Designing Filters

Additional Examples and Tutorials

Preface

About This Guide

Guide Contents

System Generator PDF Doc Set

Additional Resources

Conventions

Typographical

Online Document

Chapter 1

Introduction

The Xilinx DSP Block Set

FIR Filter Generation

Support for MATLAB

System Resource Estimation

Hardware Co-Simulation

System Integration Platform

Chapter 2

Installation

Downloading

Hardware Co-Simulation Support

System Requirements and Recommendations

Hardware Recommendations

Operating System and Software Requirements

Compatibility with Other Tools

Software Prerequisites

Using the ISE Design Suite Installer

Choosing the MATLAB Version for a Windows OS Installation

Installing System Generator On the Linux OS

Post Installation Tasks

Hardware Co-Simulation Installation

Ethernet-Based Hardware Co-Simulation

Installing the Proxy Executable for Linux Users

JTAG-Based Hardware Co-Simulation

Third-Party Hardware Co-Simulation

Compiling Xilinx HDL Libraries

ModelSim SE

Configuring the System Generator Cache