FINAL

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CHAPTER 1

INTRODUCTION

Traditional heart monitoring solutions exist for many years such as the Holter Traditional heart monitoring solutions exist for many years such as the Holter device which records the patient’s for 24 to 48 hours and is then analyzed afterwards by device which records the patient’s for 24 to 48 hours and is then analyzed afterwards by the cardiologist. The patient can ‘wear’ the device and go home and resume his/her the cardiologist. The patient can ‘wear’ the device and go home and resume his/her normal activities. The main drawback of these solutions is when a major incident occurs normal activities. The main drawback of these solutions is when a major incident occurs during the monitoring phase which is recorded but no immediate action is taken to help during the monitoring phase which is recorded but no immediate action is taken to help the user.

the user.

As our project involves the design and development of medical equipment, as a As our project involves the design and development of medical equipment, as a precautionary measure, in order to minimize failures we take some necessary steps to precautionary measure, in order to minimize failures we take some necessary steps to

intimate the respective doctors in time in case

intimate the respective doctors in time in case of emergencies using the GSM and throughof emergencies using the GSM and through short mail service and see to it

short mail service and see to it that such misfortunes are controlled and taken care.that such misfortunes are controlled and taken care. Th

The e hehearart t papatitienent t is is momoninitotorered d ususining g vavaririouous s tytypepes s of of sesensnsorors s (E(ECGCG,, acce

accelerleromeometerter, , OxyOxygengen). ). The The sensensor sor infinformormatiation on is is colcolleclected ted and and tratransfnsferrerred. ed. OneOne di

diststininctctioion n of of ouour r sosolulutition on cocompmparared ed to to ththe e ototherhers s is is ththat at we we cacan n pepersrsononalalizize e ththee monitoring and we have mechanisms in place to locate the user in case of emergency monitoring and we have mechanisms in place to locate the user in case of emergency whether the patient is indoors or outdoors. We detect life threatening arrhythmias and whether the patient is indoors or outdoors. We detect life threatening arrhythmias and give the

give the patipatient general informatent general information about ion about theitheir r healthealth h when they are when they are not in not in a dangerousa dangerous situation. We can also store extra information for further use b

situation. We can also store extra information for further use b y the health providersy the health providers The heart monitoring system designed in our project is such that if the first The heart monitoring system designed in our project is such that if the first number dialed is busy, not reachable or out of service, the second number stored will be number dialed is busy, not reachable or out of service, the second number stored will be di

dialaled ed anand d so so onon. . ThThererefeforore, e, ththis is spspececiaial l fefeataturure e of of ththe e sysyststem em mamakekes s it it momorere advantageous and preferable.

advantageous and preferable. To ensure good medical service: To ensure good medical service:

•

• be aware of patients medical record be aware of patients medical record •

• Co-operate with the various activities of the industryCo-operate with the various activities of the industry •

• Take preventive measures in a proactive way so as to provide fast and bestTake preventive measures in a proactive way so as to provide fast and best

medical service. medical service.

•

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CHAPTER 2

WORKING PRINCIPLE

2.1 Block diagram

Fig 2.1 Block diagram of system design Fig 2.1 Block diagram of system design

In the above figure heart pulses are monitored continuously. There are seven In the above figure heart pulses are monitored continuously. There are seven sensors programmed with upper and lower limits for each of them as per the user’s sensors programmed with upper and lower limits for each of them as per the user’s convenience. These sensors keep monitoring the respective parameter variations as a convenience. These sensors keep monitoring the respective parameter variations as a measure of precaution. The liquid

measure of precaution. The liquid crystal display displays the current sensor readings.crystal display displays the current sensor readings.

The sensor readings and the limits stored in the memory is compared by the The sensor readings and the limits stored in the memory is compared by the mi

micrcrococontontrorollller er eveverery y titimeme. . WhWheneneveever r ththe e rereadiadingngs s sesensnsed ed is is ouout t of of lilimimitsts, , ththee microcontroller fetches the phone number stored in the memory and gives command to microcontroller fetches the phone number stored in the memory and gives command to the GSM circuit to the dial to the concerned person. If the first number dialed is busy, out the GSM circuit to the dial to the concerned person. If the first number dialed is busy, out of reach or switched off, then the next number is dialed. Thus, the phone numbers are of reach or switched off, then the next number is dialed. Thus, the phone numbers are dialed one after the other sequentially until any of the staff is reached. At the same time, dialed one after the other sequentially until any of the staff is reached. At the same time, microcontroller will send data to the computer.

microcontroller will send data to the computer.

Microcontroller Microcontroller MEMORY MEMORY GSM Modem GSM Modem interface interface LCD LCD ADC ADC Heart pulse Heart pulse

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Depend on the data received from the microcontroller; the computer outputs the Depend on the data received from the microcontroller; the computer outputs the required message through the GSM modem to intimate the person about the patients’ required message through the GSM modem to intimate the person about the patients’ status with some appropriate message delivery. After receiving the message

status with some appropriate message delivery. After receiving the message regarding theregarding the Patient status of the device, he/she will send a code to the microcontroller to take the Patient status of the device, he/she will send a code to the microcontroller to take the necessary action. Hence controlling any furthers hazards.

necessary action. Hence controlling any furthers hazards.

2.2 Emergency Event Procedure

Fig 2.2 Emergency Event Procedures Fig 2.2 Emergency Event Procedures

Server Server Messaging Messaging System System Control Program

Control Program AlarmAlarm Cardiac Event

Cardiac Event

User User

Ambulance

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2.3 Circuit diagram

Fig 2.3 Circuit Diagram Fig 2.3 Circuit Diagram

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CHAPTER 3

SYSTEM ELEMENTS DESCRIPTION

3.1 3.1 Microcontrolle

Microcontrollerr

The 89S52 Micro-controller is heart of this project. It is the chip that processes The 89S52 Micro-controller is heart of this project. It is the chip that processes the User Data and executes the same. The software inherited in this chip manipulates the the User Data and executes the same. The software inherited in this chip manipulates the data and sends the

data and sends the result for visual display.result for visual display.

The AT89S52 is a low-power, high-performance CMOS 8-bit microcomputer The AT89S52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Flash Programmable and Erasable Read Only Memory (EPROM).

with 8K bytes of Flash Programmable and Erasable Read Only Memory (EPROM). The

The device is device is manufmanufactureactured d using Atmel’s high-densusing Atmel’s high-density ity non-vonon-volatilatile le memormemoryy technology and is compatible with the industry standard MCS-51™ instruction set and technology and is compatible with the industry standard MCS-51™ instruction set and pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or pin out. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional non-volatile memory programmer. By combining a versatile 8-bit CPU by a conventional non-volatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel’s AT89S52 is a powerful microcomputer with Flash on a monolithic chip, the Atmel’s AT89S52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control which provides a highly flexible and cost effective solution to many embedded control applications.

applications.

The AT89S52 provides the following standard features: 8K bytes of Flash, 128 The AT89S52 provides the following standard features: 8K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt bytes of RAM, 32 I/O lines, two 16-bit timer/counters, five vector two-level interrupt

architecture, a full duplex serial port, on-chip oscillator and clock circuitry. architecture, a full duplex serial port, on-chip oscillator and clock circuitry.

In addition, the AT89S52 is designed with static logic for operation down to zero In addition, the AT89S52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power down mode saves the RAM contents but freezes the to continue functioning. The Power down mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

oscillator disabling all other chip functions until the next hardware reset.

Features

•

• 8K 8K Bytes Bytes of of In-System In-System Reprogrammable Reprogrammable Flash Flash Memory Memory Endurance:Endurance: 1,000 Write/Erase Cycles

1,000 Write/Erase Cycles •

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•

• Three-Level Three-Level Program Program Memory Memory Lock Lock •

• 128 128 x x 8-Bit 8-Bit Internal Internal RAMRAM •

• 32 32 Programmable Programmable I/O I/O LinesLines •

• Two Two 16-Bit 16-Bit Timer/CountersTimer/Counters •

• Six Six Interrupt Interrupt SourcesSources •

• Programmable Programmable Serial Serial ChannelChannel •

• Low Low Power Power Idle Idle and and Power Power Down Down ModesModes

3.2 ADC 0809

The ADC0809 data acquisition component is a monolithic CMOS device with an The ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit

8-bit analoganalog-to-di-to-digital gital converconverter, ter, 8-chann8-channel el multimultiplexer plexer and and micromicroprocesprocessor sor compatcompatibleible contro

control l logiclogic. . The 8-bit The 8-bit A/D converter uses successivA/D converter uses successive e approxiapproximatimation on as the as the converconversionsion technique. The converter features a high impedance chopper stabilized comparator, a technique. The converter features a high impedance chopper stabilized comparator, a 256R voltage divider with analog switch tree and a Successive Approximation register. 256R voltage divider with analog switch tree and a Successive Approximation register.

The 8-channel multiplexer can directly access any of 8-single ended. The device The 8-channel multiplexer can directly access any of 8-single ended. The device eli

eliminminateates s the the need need for for extexternernal al zerzero o and and fulfull-l-scascale le adjadjustustmenments. ts. EasEasy y intinterferfaciacing ng toto microprocessors is provided by the latched and decoded multiplexer address inputs and microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs.

latched TTL TRI-STATE outputs.

The ADC0809 offers high speed,

The ADC0809 offers high speed, high accuracy, minimal temperaturehigh accuracy, minimal temperature

dependence, excellent long-term accuracy and repeatability, and consumes minimal dependence, excellent long-term accuracy and repeatability, and consumes minimal power. These features make this device

power. These features make this device ideally suited to applications from process andideally suited to applications from process and machine control to consumer and automotive applications.

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3.2.1 Features:

 Easy interface to all Easy interface to all microprocessorsmicroprocessors

 Operates ratio metrically or with 5 VDC or analog span adjustedOperates ratio metrically or with 5 VDC or analog span adjusted voltage reference

voltage reference

 No zero or full-scale adjust required No zero or full-scale adjust required  8-channel multiplexer with address logic8-channel multiplexer with address logic

 0V to 5V input range 0V to 5V input range with single 5V power supplywith single 5V power supply  Outputs meet TTL voltage level specificationsOutputs meet TTL voltage level specifications  Standard hermetic or molded 28-pin DIP packageStandard hermetic or molded 28-pin DIP package  28-pin molded chip carrier package28-pin molded chip carrier package

 Resolution : 8 BitsResolution : 8 Bits

 Total Unadjusted Error: ±1⁄2 LSB and ±1 LSBTotal Unadjusted Error: ±1⁄2 LSB and ±1 LSB  Single Supply: 5 VDCSingle Supply: 5 VDC

 Low Power: 15 mWLow Power: 15 mW

 Conversion Conversion Time: Time: 100 100 µsµs

3.2.2 Functional

3.2.2 Functional Description

Description

Multiplexer:

The

The devidevice ce contcontainains s an an 8-c8-chanhannel nel sinsinglegle-en-ended ded AnaAnalog log sigsignal nal mulmultiptiplexlexer. er. AA particular input channel is selected by using the address decoder. Table 1shows the input particular input channel is selected by using the address decoder. Table 1shows the input states for the address lines to select any channel. The address latched into the decoder on states for the address lines to select any channel. The address latched into the decoder on the low-to-high transition of the address latch enable signal.

the low-to-high transition of the address latch enable signal.

Converter: Converter:

The heart of this single chip data acquisition system is its 8-bit analog-to-digital The heart of this single chip data acquisition system is its 8-bit analog-to-digital converter. The converter is designed to give fast, accurate, and repeatable conversions converter. The converter is designed to give fast, accurate, and repeatable conversions over a wide range of temperatures.

over a wide range of temperatures.

The converter is partitioned into 3 major sections: The converter is partitioned into 3 major sections:  256R ladder network 256R ladder network

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 Comparator Comparator

256R Ladder Network: 256R Ladder Network:

The 256R ladder network approach is chosen so that the digital codes do not go The 256R ladder network approach is chosen so that the digital codes do not go missing (monotonic). In addition to this 256R network d

missing (monotonic). In addition to this 256R network d oes not cause load variations onoes not cause load variations on the reference voltage. The

the reference voltage. The bottom resistor and the top resistor of the ladder network arebottom resistor and the top resistor of the ladder network are not the same value

not the same value as the remainder of the network. The as the remainder of the network. The difference in these resistorsdifference in these resistors causes the output characteristic to be

causes the output characteristic to be symmetrical with the zero and full-scale points of symmetrical with the zero and full-scale points of the transfer curve. The first output transition occur when

the transfer curve. The first output transition occur when the analog signal has reachedthe analog signal has reached +1⁄2 LSB and succeeding

+1⁄2 LSB and succeeding output transitions occur every 1 LSB later up to output transitions occur every 1 LSB later up to full-scale.full-scale.

Successive Approximation Register: Successive Approximation Register:

The successive approximation register (SAR) performs 8 iterations The successive approximation register (SAR) performs 8 iterations to

to apapprproxoximimatate e ththe e ininpuput t volvoltatage. ge. In In ththe e ADADC0C080808, 8, ADADC0C0809809, , ththee approximation technique is extended to 8 bits using the 256R network. approximation technique is extended to 8 bits using the 256R network.

The A/D converter’s successive approximation register (SAR) is reset on the The A/D converter’s successive approximation register (SAR) is reset on the posit

positive edge ive edge of the of the starstart conversion (SC) pulse. The t conversion (SC) pulse. The converconversion is sion is begun on begun on the fallingthe falling edge of the start conversion pulse. A conversion in process will be interrupted by receipt edge of the start conversion pulse. A conversion in process will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying of a new start conversion pulse. Continuous conversion may be accomplished by tying the end-of-conversion (EOC) output to the SC input. If used in this mode, an external the end-of-conversion (EOC) output to the SC input. If used in this mode, an external start convers

start conversion pulse ion pulse should be should be applieapplied d after power up. after power up. End-ofEnd-of-conve-conversion will go rsion will go lowlow between 0 and 8 clock pulses after the rising edge of start conversion.

between 0 and 8 clock pulses after the rising edge of start conversion.

Comparator: Comparator:

The most important section of the A/D converter is the comparator. It is this The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate accuracy of the entire converter. It is also section which is responsible for the ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the repeatability of the device. A the comparator drift which has the greatest influence on the repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all the chopper-stabilized comparator provides the most effective method of satisfying all the converter requirements. The chopper-stabilized comparator converts the DC input signal converter requirements. The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through a high gain AC amplifier and has the into an AC signal. This signal is then fed through a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the DC level restored. This technique limits the drift component of the amplifier since the

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drift is a DC component which is not passed by the AC amplifier. This makes the entire drift is a DC component which is not passed by the AC amplifier. This makes the entire A/D converter extremely insensitive to temperature, long term drift and input offset error. A/D converter extremely insensitive to temperature, long term drift and input offset error.

Ratio metric conversion: Ratio metric conversion:

The ADC0808, ADC0809 is designed as a complete Data Acquisition System The ADC0808, ADC0809 is designed as a complete Data Acquisition System (DAS) for ratio metric conversion systems. In ratio metric systems, the physical variable (DAS) for ratio metric conversion systems. In ratio metric systems, the physical variable being measured is expressed as a percentage of full-scale which is not necessarily related being measured is expressed as a percentage of full-scale which is not necessarily related to an absolute standard. The voltage input to the ADC0808 is expressed by the equation, to an absolute standard. The voltage input to the ADC0808 is expressed by the equation,

V

Viinn == DDxx V

Vffss--VVzz DDmmaaxx--DDmmiinn VIN=Input voltage into the ADC0808 VIN=Input voltage into the ADC0808 Vfs=Full-scale voltage

Vfs=Full-scale voltage VZ=Zero voltage VZ=Zero voltage

DX=Data point being measured DX=Data point being measured DMAX=Maximum data limit DMAX=Maximum data limit DMIN=Minimum data limit DMIN=Minimum data limit

A good example of a ratio metric transducer is a potentiometer used as a position A good example of a ratio metric transducer is a potentiometer used as a position sensor. The position of the wiper is directly proportional to the output voltage which is a sensor. The position of the wiper is directly proportional to the output voltage which is a ratio of the full-scale voltage across it. Since the data is represented as a proportion of ratio of the full-scale voltage across it. Since the data is represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large source of error full-scale, reference requirements are greatly reduced, eliminating a large source of error and cost for many applications. A major advantage of the ADC0808, ADC0809 is that and cost for many applications. A major advantage of the ADC0808, ADC0809 is that the input voltage range is equal to the supply range so the transducers can be connected the input voltage range is equal to the supply range so the transducers can be connected directly across the supply and their outputs connected directly into the multiplexer inputs. directly across the supply and their outputs connected directly into the multiplexer inputs. Rat

Ratio io metmetric ric tratransdnsducerucers s sucsuch h as as potpotententiomiometeeters, rs, strstrain ain gauggauges, es, thethermirmistostor r bribridgedges,s, pressure transducers, etc., are suitable for measuring proportional relationships; however, pressure transducers, etc., are suitable for measuring proportional relationships; however, many types of measurements must be referred to an absolute standard such as voltage or many types of measurements must be referred to an absolute standard such as voltage or current.

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3.3

3.3 3.3 LIQUID CRYSTAL DISPLAY (LCD)

3.3 LIQUID CRYSTAL DISPLAY (LCD)

A Liquid crystal display (LCD) is a low cost, low power device capable of A Liquid crystal display (LCD) is a low cost, low power device capable of displaying text and images. LCDs are extremely common in embedded systems, since displaying text and images. LCDs are extremely common in embedded systems, since suc

such h sysystestems ms oftoften en do do not have not have vidvideo eo monmonititors like ors like thothose se thathat t comcome e stastandarndard d witwithh desktop systems. LCDs can be found in numerous common devices like watches, fax and desktop systems. LCDs can be found in numerous common devices like watches, fax and copy machines, and calculators.

copy machines, and calculators.

The LCD controller provides a relatively simple interface between a processor The LCD controller provides a relatively simple interface between a processor and an LCD. LCDs can be added quite easily to an application and use as few as three and an LCD. LCDs can be added quite easily to an application and use as few as three digital output pins for control.

digital output pins for control.

Communication bus Communication bus

Figure 3.1 Schematic diagram of an LCD Figure 3.1 Schematic diagram of an LCD

There are different types of LCDs such as reflective LCD, absorption LCD, dot There are different types of LCDs such as reflective LCD, absorption LCD, dot matrix LCD. Each type of LCD is able to display multiple characters. In addition, each matrix LCD. Each type of LCD is able to display multiple characters. In addition, each char

charactacter er may be may be disdisplaplayed in yed in nornormal or mal or invinverterted ed fasfashiohion. n. The LCD The LCD may permimay permit t aa Microcontroller Microcontroller LCD controller LCD controller E E R/W R/W R/S R/S DB7-DB0 DB7-DB0

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char

charactacter er to to be be bliblinkinking ng or or may permimay permit t disdisplaplay y of of a a curcursor indicsor indicatiating ng thethe” ” curcurrenrent”t” character. Such functionality would be difficult to be implemented using software.

character. Such functionality would be difficult to be implemented using software.

Thus, an LCD controller is used to provide a simple interface to an LCD, perhaps Thus, an LCD controller is used to provide a simple interface to an LCD, perhaps eight data inputs and one enable input. This byte may be a control word, which can be an eight data inputs and one enable input. This byte may be a control word, which can be an instruction or data word.

instruction or data word.

The most common connector used for the 44780 based LCDs is 14 pins in a row, The most common connector used for the 44780 based LCDs is 14 pins in a row, with pin centers 0.100" apart. The pins are wired as:

with pin centers 0.100" apart. The pins are wired as:

P

Piinnss DDeessccrriippttiioonn

1

1 GGrroouunndd 2

2 VVcccc

3

3 CCoonnttrraasst t VVoollttaaggee 4

4 ""RR//SS" " __IInnssttrruuccttiioonn//RReeggiisstteer r SSeelleecctt 5

5 ""RR//WW" " __RReeaadd//WWrriitte e LLCCD D RReeggiisstteerrss 6

6 ""EE"" CClloocckk 7

7 – – 1144 DDaatta a II//O O PPiinnss

Table 3.2 shows the pin description of 16

x

2 LCD2 LCD

From this description we can observe that, the interface is a parallel bus, allowing From this description we can observe that, the interface is a parallel bus, allowing simple and fast reading/writing of data to and

simple and fast reading/writing of data to and from the LCD.from the LCD.

3.4 I

22

C BUS

II22_{C stands for inter-integrated circuit. This was designed by Philips but now a}_{C stands for inter-integrated circuit. This was designed by Philips but now a} number of semiconductor device manufacturers are making devices compatible with I number of semiconductor device manufacturers are making devices compatible with I22_C_C bus.

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This I

This I22_{C bus is used mainly with single-chip micro controller based systems that}_{C bus is used mainly with single-chip micro controller based systems that} re

reququirire e gegenerneralal-pu-purprposose e cicircrcuiuits ts lilike ke EEEEPRPROMOM, , RARAM, M, rereal al titime me clclockock, , LCLCD D && audio/video tuning circuits. A key advantage of this is that only two lines can connect audio/video tuning circuits. A key advantage of this is that only two lines can connect multiple devices. All devices have built-in addresses.

multiple devices. All devices have built-in addresses.

Figure 3.3 shows a master connected to various devices using I2C Figure 3.3 shows a master connected to various devices using I2C..

In circuit with multiple devices, one device (usually the micro controller) takes In circuit with multiple devices, one device (usually the micro controller) takes the role of master. Another device (only one of the multiple devices at any one time) acts the role of master. Another device (only one of the multiple devices at any one time) acts as a slave device. Master device takes control of SCL; i.e. SCL is set low or high under as a slave device. Master device takes control of SCL; i.e. SCL is set low or high under the control of master (usually micro controller). Slave device accepts the data from micro the control of master (usually micro controller). Slave device accepts the data from micro controller (e.g. writing into memory) or sends the data to micro controller (reading from controller (e.g. writing into memory) or sends the data to micro controller (reading from memory) under the control of master device.

memory) under the control of master device. Four different conditions exist in I

Four different conditions exist in I22_{C bus transfers. These are START, STOP, BIT}_{C bus transfers. These are START, STOP, BIT} TRANSFER (read/write) & ACKNOWLEDGE.

TRANSFER (read/write) & ACKNOWLEDGE.

Normal data bit write/read

Dur

During ing trtransansfer fer of of datdata a frofrom m masmaster ter (mi(micro cro concontrotrolleller) r) to to slaslave ve devdevice ice (e.(e.g.g. EEPROM), SDA is set to logic’0’ or logic’1’ only when SCL is low. After small delay, EEPROM), SDA is set to logic’0’ or logic’1’ only when SCL is low. After small delay, SCL is pulsed high to clock in data. During read operation, SDA is an input line & its SCL is pulsed high to clock in data. During read operation, SDA is an input line & its logic state is clocked in with SCL going high. Master (micro controller) can then read the logic state is clocked in with SCL going high. Master (micro controller) can then read the level of SDA.

level of SDA.

Start condition Start condition

Start is a special condition where SDA changes its state from high to low when Start is a special condition where SDA changes its state from high to low when SCL is high. Both SCL & SDA are

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Stop condition Stop condition

Stop is also a special condition where SDA goes from low to high when SCL is Stop is also a special condition where SDA goes from low to high when SCL is high. Both SCL & SDA are controlled by master (micro controller).

high. Both SCL & SDA are controlled by master (micro controller).

Acknowledge Acknowledge

Aft

After er tratransmnsmittitting ing eigeight ht datdata a bitbits s frofrom m micmicro ro concontrotrolleller r to to the the devdevice ice (e.(e.g.g. EEPROM), direction of SDA line is reversed. One more clock pulse is given by micro EEPROM), direction of SDA line is reversed. One more clock pulse is given by micro controller. During this period, the slave device sets SDA to low. This indicates the controller. During this period, the slave device sets SDA to low. This indicates the acceptance of data by receiving device (e.g. EEPROM). When data is read from slave acceptance of data by receiving device (e.g. EEPROM). When data is read from slave device (e.g. EEPROM), after reading eight bits, direction of SDA is reversed. SDA is set device (e.g. EEPROM), after reading eight bits, direction of SDA is reversed. SDA is set low (to send acknowledge) or high (to send no-acknowledge) & then SCL is pulsed

low (to send acknowledge) or high (to send no-acknowledge) & then SCL is pulsed

How to write a byte in EEPROM?

Typical example of writing into memory (device address A0 hex) location 58 Typical example of writing into memory (device address A0 hex) location 58 (hex) with data byte 30 (hex) is given below:

(hex) with data byte 30 (hex) is given below:

S10100000A01011000A00110000AP S10100000A01011000A00110000AP Where, Where, S – Start S – Start P – Stop P – Stop A – Acknowledge A – Acknowledge 1 & 0 – Data bits 1 & 0 – Data bits

Description of the above sequence

Description of the above sequence is as follows:is as follows:



 AcActition on is is ststararteted d wiwith th ststarart t concondiditition on gengenereratated ed by by mamastster er (m(micicroro controller).

controller). 

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

 EEPROM responds with acknowledge during next clock pulse.EEPROM responds with acknowledge during next clock pulse. 

 0101 1000 (58h) is transmitted as byte address with EEPROM.0101 1000 (58h) is transmitted as byte address with EEPROM. 

 Again EEPROM responds with acknowledge during next clock pulse.Again EEPROM responds with acknowledge during next clock pulse. 

 Finally data byte 0011 0000 (30h) is Finally data byte 0011 0000 (30h) is transmitted.transmitted. 

 EEPROM acknowledges during next clock pulse.EEPROM acknowledges during next clock pulse. 

 At the end, master (micro controller) generates stop condition.At the end, master (micro controller) generates stop condition.

3.5 EEPROM

The Microchip Technology Inc. 24LC04B/08B is a 4Kbit or 8Kbit electrically The Microchip Technology Inc. 24LC04B/08B is a 4Kbit or 8Kbit electrically erasable PROM (EEPROM). The device is organized as two or four blocks of 256-x 8-bit erasable PROM (EEPROM). The device is organized as two or four blocks of 256-x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 memory with a 2-wire serial interface. Low voltage design permits operation down to 2.5 volts with typical standby and active currents of only 5 mA and 1 mA respectively. The volts with typical standby and active currents of only 5 mA and 1 mA respectively. The 24L

24LC0C04B4B/0/08B 8B alalso so has has a a papagege-wr-writite e cacapabpabililitity y fofor r up up to to 16 16 bybytetes s of of dadatata. . ThThee 24LC04B/08B is available in the standard 8-pin DIP, 8-lead surface mount SOIC, MSOP 24LC04B/08B is available in the standard 8-pin DIP, 8-lead surface mount SOIC, MSOP and TSSOP packages.

and TSSOP packages.

3.5.1 Features

•

• Single supply with operation down to 2.5VSingle supply with operation down to 2.5V •

• Low power CMOS technologyLow power CMOS technology •

• 1 mA active current typical1 mA active current typical •

• 10 micro ampere standby current typical at 5.5V10 micro ampere standby current typical at 5.5V •

• 5 micro ampere standby current typical at 3.0V5 micro ampere standby current typical at 3.0V •

• Organized as two or four blocks oOrganized as two or four blocks of 256 bytesf 256 bytes •

• 2-wire serial interface bus, I2C™ compatible2-wire serial interface bus, I2C™ compatible •

• Schmitt trigger, filtered inputs for noise Schmitt trigger, filtered inputs for noise SuppressionSuppression •

• Output slope control to eliminate ground bounceOutput slope control to eliminate ground bounce •

• 100 kHz (E-temp) and 400 100 kHz (E-temp) and 400 kHz (C/I-temp.) CompatibilitykHz (C/I-temp.) Compatibility •

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•

• Page-write buffer for up to 16 bytesPage-write buffer for up to 16 bytes •

• 2 ms typical write cycle time for page-write2 ms typical write cycle time for page-write •

• Hardware write protect for entire memoryHardware write protect for entire memory •

• Can be operated as a serial ROMCan be operated as a serial ROM •

• Factory programming (QTP) availableFactory programming (QTP) available •

• ESD protection > 4,000VESD protection > 4,000V •

• 1,000,000 erase/write cycles ensured1,000,000 erase/write cycles ensured •

• Data retention > 200 yearsData retention > 200 years

3.5.2 Functional

3.5.2 Functional Description

Description

The 24LC04B/08B supports a bi-directional 2-wire bus and data transmission The 24LC04B/08B supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter and if receiving protocol. A device that sends data onto the bus is defined as transmitter and if receiving data, as receiver. The bus has to be controlled by a master device which generates the data, as receiver. The bus has to be controlled by a master device which generates the se

seririal al clclocock k (S(SCLCL), ), cocontntrorols ls ththe e bubus s accaccesess s anand d gegeneneraratetes s ththe e STSTART ART anand d STSTOPOP conditions, while the 24LC04B/08B works as slave. Both master and slave can operate as conditions, while the 24LC04B/08B works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which

transmitter or receiver, but the master device determines which mode is activated.mode is activated.

Bus Characteristics Bus Characteristics

The bus protocols are defined as: The bus protocols are defined as:

 Data transfer may be initiated only when the bData transfer may be initiated only when the bus is not busyus is not busy

 During data transfer, the data line must remain stable whenever the clock During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition defined.

a START or STOP condition defined.

Bus Conditions: Bus Conditions: Bus not Busy (A) Bus not Busy (A)

Both data and clock lines remain HIGH. Both data and clock lines remain HIGH.

Start Data Transfer (B) Start Data Transfer (B)

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A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH det

deterermimines a nes a STSTARART T cocondndititioion. n. AlAll l cocommmmanands ds mumust be st be prpreceecededed d by a by a STSTARARTT condition.

condition.

Stop Data Transfer (C) Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. determines a STOP condition. All operations must be ended with a STOP condition.

Data Valid (D) Data Valid (D)

The state of the data line represents valid data when, after a START condition, The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be

the line must be changed during the LOW period of changed during the LOW period of the clock signal. There is one the clock signal. There is one clock clock pu

pulslse e peper r bibit t of of datdata. a. EaEach ch dadata ta trtranansfsfer er is is ininititiaiated ted wiwith th a a STSTARART T cocondndititioion n andand terminated with a STOP condition. The number of the data bytes transferred between the terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions are determined by the

START and STOP conditions are determined by the master device.master device.

Acknowledge Acknowledge

Each receiving device, when addressed, is obliged to generate an acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges, has to pull which is associated with this acknowledge bit. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.

the master to generate the STOP condition.

Device Addressing Device Addressing

A control byte is the first byte received following the start condition from the A control byte is the first byte received following the start condition from the master device. The control byte consists of a 4-bit control code, for the 24LC04B/08B master device. The control byte consists of a 4-bit control code, for the 24LC04B/08B this is set as 1010 binary for read and writes operations. The next three bits of the control this is set as 1010 binary for read and writes operations. The next three bits of the control byte are the block select bits (B2, B1, and B0). B2 is a ‘don't care’ for both the 24LC04B byte are the block select bits (B2, B1, and B0). B2 is a ‘don't care’ for both the 24LC04B and 24LC08B; B1 is a ‘don't care’ for the 24LC04B. The master device to select which of and 24LC08B; B1 is a ‘don't care’ for the 24LC04B. The master device to select which of

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the two uses them or four 256-word blocks of memory are to be accessed. These bits are the two uses them or four 256-word blocks of memory are to be accessed. These bits are in effect the most significant bits of the word address. The last bit of the control byte in effect the most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to ‘1’, a read operation is selected and defines the operation to be performed. When set to ‘1’, a read operation is selected and whe

when n seset t to to ‘0‘0’, ’, a a wrwritite e opopereratatioion n is is seselelectcteded. . FoFollllowowining g ththe e ststarart t cocondindititionon, , ththee 24L

24LC0C04B4B/0/08B 8B momoninitotors rs ththe e SDSDA A bubus s checheckckining g ththe e dedevivice ce tytype pe ididenentitififier er bebeiningg transmitted. Upon a 1010 code, the slave device outputs an acknowledge signal on the transmitted. Upon a 1010 code, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC04B/08B will select a read or SDA line. Depending on the state of the R/W bit, the 24LC04B/08B will select a read or write operation.

write operation.

3.6 GSM MODEM

GSM is a most demanding system with the full range of digital techniques, via, GSM is a most demanding system with the full range of digital techniques, via, equalization, frequency, hopping, sophisticated speech coding, error correction coding, equalization, frequency, hopping, sophisticated speech coding, error correction coding, echo cancellation block interleaving and advanced modulation provided to maximize the echo cancellation block interleaving and advanced modulation provided to maximize the performance. The degree of processing is such that the battery current drain of the performance. The degree of processing is such that the battery current drain of the

integrated circuits in the mobile is comparable with the

integrated circuits in the mobile is comparable with the current required to provide the RFcurrent required to provide the RF power for the

power for the transmitter.transmitter.

The GSM air interface provides the physical link between the mobile and the The GSM air interface provides the physical link between the mobile and the network. GSM is a digital system employing time division multiple access (TDMA) network. GSM is a digital system employing time division multiple access (TDMA) tec

technihnique que and and operoperateates s at at 900 900 MHzMHz. . The The CEPCEPT(cT(confonfereerence nce of of EurEuropeopean an post andpost and telecommunication) has made available two frequency bands in the GSM system : (1) telecommunication) has made available two frequency bands in the GSM system : (1) 890 MHz for the mobile to base station (up link), and (2) 985 MHz to 960 MHz for the 890 MHz for the mobile to base station (up link), and (2) 985 MHz to 960 MHz for the base station to mobile (down link).These 25 MHz bands are divided into 124 pairs of base station to mobile (down link).These 25 MHz bands are divided into 124 pairs of carriers spaced by 200 MHz . Each of the carriers is divided into 8 TDMA time slots of carriers spaced by 200 MHz . Each of the carriers is divided into 8 TDMA time slots of 0.577 m sec length, such that the frame length is 4.615 m sec. the recurrence of each time 0.577 m sec length, such that the frame length is 4.615 m sec. the recurrence of each time slot makes up one physical channel, such that each carrier can support eight physical slot makes up one physical channel, such that each carrier can support eight physical channels, both in up link & down link directions.

channels, both in up link & down link directions.

3.6.1 GSM Architecture

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The basic architecture of different cellular standards is the same,

The basic architecture of different cellular standards is the same, their individualtheir individual components and configuration may differ drastically. Basic components of GSM include components and configuration may differ drastically. Basic components of GSM include Base transceiver station (BTS), base station controller, mobile switching control (MSC) Base transceiver station (BTS), base station controller, mobile switching control (MSC) and the variety of registers and network managemen

and the variety of registers and network managemen t systems.t systems.

Fig 3.4 GSM Architecture Fig 3.4 GSM Architecture

The mobile station comprises mobile equipment and a subscriber identity module The mobile station comprises mobile equipment and a subscriber identity module (SIM) security and authentication or subscriber. The BTS and BSC together constitute (SIM) security and authentication or subscriber. The BTS and BSC together constitute the base station subsystem (BSS) and perform all the functions related to the radio the base station subsystem (BSS) and perform all the functions related to the radio channel for speech data signaling and frequency hopping control and power level control. channel for speech data signaling and frequency hopping control and power level control. The MSC, VLR and HLR are concerned with mobility management functions these The MSC, VLR and HLR are concerned with mobility management functions these includes authentication and registration of a mobile customers, location updating call includes authentication and registration of a mobile customers, location updating call setup and release.

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Th

The e HLHLR R is is ththe e mamastster er susubsbscrcribiber er datdatababasase e anand d cacarrrrieier r ininfoformrmatatioion n ababoutout ind

indiviividual dual subsubscrscribeiber r numnumberbers. s. SubSubscrscriptiption ion levlevelsels, , calcall l resrestritrictictions ons suppsupplemlemententaryary ser

servicvices es and and the most the most recrecent locatent location ion of of subsubscrscribeiber. r. The The VLR acts VLR acts as as a a temtemporporaryary subs

subscricriber ber datdatabaabase se for for all all subsubscrscribeibers rs and and concontaitains ns simsimilailar r infinformormatiation on as as thathat t inin HLR.VLR obviates a need of the MCS to access the HLR for energy transaction. The HLR.VLR obviates a need of the MCS to access the HLR for energy transaction. The authentification centre (AUC) works closely with the HLR and

authentification centre (AUC) works closely with the HLR and provides the informationprovides the information to authenticator all cells in order to guard against fraud. The equipment identity register to authenticator all cells in order to guard against fraud. The equipment identity register (E

(EIRIR) ) is is usused ed fofor r eqequiuipmpment ent sesecucuririty ty anand d vavalilidatdatioion n of of didiffffererenent t tytypepes s of of momobibilele equipment.

equipment.

Network management is used to monitor and control the major elements of the Network management is used to monitor and control the major elements of the GSM network. In particular it monitors and reports faults and performance data besides GSM network. In particular it monitors and reports faults and performance data besides helping in reconfiguration of network. GSM also defines several interfaces which include helping in reconfiguration of network. GSM also defines several interfaces which include the radio interface, the interface between MSC and BSC, the interface for external data the radio interface, the interface between MSC and BSC, the interface for external data device and signaling interface which

device and signaling interface which allows roaming between different GSM networks.allows roaming between different GSM networks.

3.6.2 Features of GSM

Th

The e prprimimarary y objobjecectitive ve of of GSGSM M is is to to prprovovidide e a a fufull ll roroamamining g momobibilele telephony service. Three broad categories

telephony service. Three broad categories of service provided by GSM areof service provided by GSM are  Tele servicesTele services

 Bearer servicesBearer services

 Supplementary servicesSupplementary services

Tele Services Tele Services

Te

Tele le seservrvicices es arare e ththe e seservrvicices es ththat at arare e prprovovidided ed on on a a ususer er tetermrmininal al babasisis.s. Paramount tele services include voice communication and facsimile transmission.

Paramount tele services include voice communication and facsimile transmission.

Bearer Services Bearer Services

Fo

For r BeBeararer er seservrviciceses, , ththe e tetermrmininal al eqequiuipmpment ent is is prproviovideded d by by ththe e ususerer, , ththee responsibility of the network service provide ending at the point of Connection. Data responsibility of the network service provide ending at the point of Connection. Data rates between 300 and

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Supplementary Services Supplementary Services

Supplementary services will be developed along the lines of ISDN services but Supplementary services will be developed along the lines of ISDN services but will vary from country to country. GSM uses ISO and OSI model.

will vary from country to country. GSM uses ISO and OSI model.

3.6.3 Working Principle

When you dial a number on the keypad of the phone, the handset transmits the When you dial a number on the keypad of the phone, the handset transmits the digits, through the built-in radio transceiver, to a nearby cell. A group of transceiver digits, through the built-in radio transceiver, to a nearby cell. A group of transceiver station is controlled by a base station controller, which in turn is connected to a mobile station is controlled by a base station controller, which in turn is connected to a mobile switching centre. The MSC, in turn, is linked

switching centre. The MSC, in turn, is linked to other cellular and fixed line nto other cellular and fixed line networks.etworks. All the switching functions within a GSM network are handled by MSC, which is All the switching functions within a GSM network are handled by MSC, which is the intelligence of the network and performs function like call routing, cell control, the intelligence of the network and performs function like call routing, cell control, switching, plus all accounting and charging activities.

switching, plus all accounting and charging activities.

Once a cell is forwarded MSC, it determines how to route the call and set up the Once a cell is forwarded MSC, it determines how to route the call and set up the required link to enable the conversation. If the call is destined for a fixed the MSC sends required link to enable the conversation. If the call is destined for a fixed the MSC sends it to DoT’s public telephone exchange, over a leased line, which then switches the call to it to DoT’s public telephone exchange, over a leased line, which then switches the call to the desired telephone. However, if the call is destined for another mobile phone, things the desired telephone. However, if the call is destined for another mobile phone, things become more complicated. First, the MSC has to figure out where the desired mobile become more complicated. First, the MSC has to figure out where the desired mobile phone is, and then

phone is, and then forward the call to the cell which forward the call to the cell which is nearest to it.is nearest to it.

But how does the MSC figure out where a particular cell phone is? It is assisted But how does the MSC figure out where a particular cell phone is? It is assisted by cellphone in this task. When the handset is powered on, it initializes itself and scans by cellphone in this task. When the handset is powered on, it initializes itself and scans the control channels. These control channels are special RF used by the cell transmitter to the control channels. These control channels are special RF used by the cell transmitter to send and receive control data. Based on the strength of received signal, the handset send and receive control data. Based on the strength of received signal, the handset assigns itself to a specific cell. In this process it informs the cell of its location so that it assigns itself to a specific cell. In this process it informs the cell of its location so that it can be passed out the handset keeps monitoring the data which is sent on the control can be passed out the handset keeps monitoring the data which is sent on the control channel till its own ID is paged-and

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However, if hand set is mobile, that is ,if the user is travelling by car while However, if hand set is mobile, that is ,if the user is travelling by car while calling, the cellular system als

calling, the cellular system also needs to keep track of the phone and o needs to keep track of the phone and the call is progress,the call is progress, so that it can automat

so that it can automatically swically switch the call to anotheitch the call to another cell as the caller moves r cell as the caller moves from onefrom one area to another. This process of switching calls between cells is user transparent, and is area to another. This process of switching calls between cells is user transparent, and is called cell hand off.

called cell hand off.

3.6.4 Strength of GSM

GSM is the first to apply the TDMA scheme developed

GSM is the first to apply the TDMA scheme developed for mobile radio systems.for mobile radio systems. It has several distinguishing features,

It has several distinguishing features, 

 Roaming in European countries.Roaming in European countries. 

 Connection to ISDN through RS box.Connection to ISDN through RS box. 

 Use of SIM cards.Use of SIM cards. 

 Control of transmission power.Control of transmission power. 

 Frequency hopping.Frequency hopping. 

 Discontinuous transmission.Discontinuous transmission. 

 Mobile assisted handover.Mobile assisted handover.

F

Frreeqquueennccyy RRaannggee GSM400

GSM400 45450.0.4 4 - - 45457.7.6 6 MHMHz z papairired ed wiwith th 46460.0.4 4 - - 46467.7.6 6 MHMHzz or

or

478.8 - 486 MHz paired with 488.8 - 496 MHz 478.8 - 486 MHz paired with 488.8 - 496 MHz GSM 850

GSM 850 824 - 849 MHz paired with 869 - 894 MHz824 - 849 MHz paired with 869 - 894 MHz GSM900

GSM900 880 - 915 MHz paired with 925 - 960 MHz880 - 915 MHz paired with 925 - 960 MHz GSM1800

GSM1800 1710 - 1785 MHz paired with 1805 - 1880 MHz1710 - 1785 MHz paired with 1805 - 1880 MHz GSM1900

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Table 3.5 Frequency Ranges Table 3.5 Frequency Ranges

TDMA Structure

TDMA Structure 8 time slots per radio carrier.8 time slots per radio carrier.

Time slot

Time slot 0.577 ms0.577 ms

Frame interval

Frame interval 8 time slots = 4.61 ms.8 time slots = 4.61 ms.

Radio carrier number

Radio carrier number 12124 4 raradidio o cacarrrrieiers rs (9(93535-9-96060MHMHzz Downlink, 890-915 MHz uplink).

Downlink, 890-915 MHz uplink).

Modulation scheme

Modulation scheme GaGausussisian an mimininimumum m shshifift t keykeyiningg with BT=0.3.

with BT=0.3.

Frequency Hopping

Frequency Hopping SSlloow w ffrreeqquueennccy y hhooppppiinngg (21740ps/s)

(21740ps/s)

Equalizer

Equalizer EqEquaualilizazatition on up up to to 16 16 mimicrcro o sesecc time dispersion.

time dispersion.

Table 3.6 Summary of Physical Layer Parameters Table 3.6 Summary of Physical Layer Parameters

3.6.5 AT

COMMANDS

The AT commands used in our project are: The AT commands used in our project are:

1.

1. ATAT (Testing for AT commands)(Testing for AT commands)

2.

2. ATE0ATE0 (Command used to determine whether or not the modem echoes(Command used to determine whether or not the modem echoes characters received by an external application (DTE)) (Possible response is characters received by an external application (DTE)) (Possible response is ‘OK’ i.e, done)

‘OK’ i.e, done)

3.

3. AT+CSMS=0AT+CSMS=0 (SMS AT command Phase2 Version 4.7.0)(SMS AT command Phase2 Version 4.7.0) (Command to select message service)

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(Possible response is +CSMS:1,1,1 OK) (Possible response is +CSMS:1,1,1 OK) (i.e.

(i.e. SMS-SMS-M0(orM0(originaiginated),ted),SMS-MSMS-MT(teT(terminarminated ted short short messamessage) ge) & & SMS- SMS-CB(cell broadcast message services) are supported)

CB(cell broadcast message services) are supported)

4.

4. AT+CMGF=1AT+CMGF=1 (command to set text mode) response OK (command to set text mode) response OK

5.

5. AT+CNMAT+CNMI=2, I=2, 1,0,0,01,0,0,0 (co(commammand nd to to selselect ect the the proproceducedure re for for mesmessagsagee reception from the network. Possible response is OK.)

reception from the network. Possible response is OK.) (AT+CMTI: “SM”,1 will be sent whenever a new message

(AT+CMTI: “SM”,1 will be sent whenever a new message is received)is received)

6.

6. AT+CMGR=1AT+CMGR=1 (command to read a message)(command to read a message)

7.

7. AT+CMGD=1AT+CMGD=1 (command to delete one or several messages)(command to delete one or several messages)

8.

8. AT+CMGS=<length><CR><PDU><ctrl-Z>AT+CMGS=<length><CR><PDU><ctrl-Z>

(Command to send a message in

(Command to send a message in PDU mode)PDU mode) (Response + CMGS :< mr> OK)

(Response + CMGS :< mr> OK)

Algorithm for initializing the modem:

Checking for AT command:

1

1.. SSeennd d ““AA””.. 2

2.. RReecceeiivve a e a cchhaarraacctteer r bbyyttee.. 3

3.. SSeennd d ““TT””.. 4

4.. RReecceeiivve e a a cchhaarraacctteer r bbyyttee 5

5.. SSeennd d 00xx00DD.. 6

6.. SSeennd d 00xx00AA.. 7

7.. RReecceeiivve 6 e 6 bbyyttees s ffrroom m tthhe me mooddeemm 8

8.. IIf f 66thth_{byte is “K”, the AT is OK. Else, a}_{byte is “K”, the AT is OK. Else, again reinitialize.}_{gain reinitialize.} 9

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Removing the echo character: Removing the echo character:

Send “ATE0” Send “ATE0” 1 1.. SSeennd d 00xx00DD.. 2 2.. SSeennd d 00xx00AA.. 3.

3. ReRececeivive the the se strtrining frg from om ththe me modeodem, m, untuntil il 0d c0d comomes es and and ststorore ie it it in a an a arrrrayay.. 4.

4. In tIn the she stotorered ard arraray, cy, cheheck fck for “or “K”K”. If K i. If K is prs presesenent, tt, thehen ecn echo iho is res remomoveved,d, Else, go to reinitialize the modem.

Else, go to reinitialize the modem. 5

5. . GGiivve e a a ddeellaay y oof f 1 1 sseeccoonndd..

Setting Message Service: Setting Message Service:

1 1.. SSeennd d ““AATT++CCSSMMSS==00”” 2 2.. SSeennd d 00xx00DD 3 3.. SSeennd d 00xx00AA 4.

4. ReRececeivive bye bytetes frs from tom the mhe mododem aem and snd stotore ire in an an an arrrray ay ununtitil 0Dl 0Dh coh comemes.s. 5

5.. SSeeaarrcch h ffoor r ““KK” ” iin n tthhe e aarrrraayy.. 6

6.. IIf f ““KK” ” iis s pprreesseenntt, , tthheen n CCSSMMS S iis s sseett.. 7.

7. ElElse se CSCSMS MS iis s nonot t ssetet. . AAgagain in rreieininittiaialilizeze.. 8

8.. DDeellaay y 1 1 sseeccoonndd..

Setting the text command: Setting the text command:

1 1.. SSeennd “d “AATT++CCMMGGFF==11””.. 2 2.. SSeennd d 00xx00DD.. 3 3.. SSeennd d 00xx00AA.. 4.

4. ReRececeivive the the che chararacacteters frs frorom thm the moe modedem anm and std storore in ae in an arn arraray any and chd chececk k for “K”.

for “K”. 5.

5. If If ““K” K” is is prpresesenent, t, tthehen tn texext t memesssasage ge is is OKOK.. 6

6.. EEllssee, r, reeiinniittiiaalliizze te thhe me mooddeemm 7

7.. DDeellaay y 1 1 sseeccoonndd..

Enabling for SMS: Enabling for SMS:

1

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2

3.. SSeennd d 00xx00AA.. 4.

4. ReRececeivive the the che chararacacteters frs frorom thm the moe modedem anm and std storore in ae in an arn arraray any and chd chececk k for “K”. If “K” is present then modem is initialized completely.

for “K”. If “K” is present then modem is initialized completely. 5

5.. EEllsse ge gootto ro reeiinniittiiaalliizze te thhe me mooddeemm..

Receiving the SMS Number from the modem: Receiving the SMS Number from the modem:

1

1.. KKeeeep op on rn reecceeiivviinng bg byyttees us unnttiil ‘l ‘+ ‘+ ‘ccoommeess.. 2.

2. WhWhen en ‘‘+’ +’ cocomemes ts thehen sn statart rt ststororining tg the he bybytetes is in an an an arrrray ay up up to to 1212ththbyte.byte. 3

3.. TThhe e 1122ththbyte is the SMS No.byte is the SMS No. 4.

4. WhWhenenevever er a Sa SMS MS is is rerececeivived ed we we rerececeivive Ae AT+T+CMCMTITI: “: “SMSM”, ”, 1.1.

Reading the SMS Received: Reading the SMS Received:

1

1.. SSeennd d ““AATT++CCMMGGRR==”” 2

2.. GGiivve e ddeellaay y oof f 11mmiilllliisseeccoonndd.. 3 3.. SSeennd d tthhe e SSMMS S NNuummbbeerr.. 4 4.. SSeennd d 00xx00DD.. 5 5.. SSeennd d 00xx00AA.. 6

6.. RReecceeiivve e bbyyttees s uunnttiil l ‘‘11’ ’ ccoommeess.. 7.

7. AfAftter geer gettttining g ‘1‘1’ st’ starart stt stororiing thng the e rrececeieiveved d bybytetes in an ars in an arraray unty untiil ‘”’l ‘”’ comes.

comes. 8

8.. TThhiis is is ts thhe se seennddeerr’’s ps phhoonne ne nuummbbeerr.. 9

9.. CCoonnttiinnuue re reecceeiivviinng ug unnttiil * l * ccoommeess.. 10.

10. StaStart rt stostoriring tng the che charharactacter er aftafter er * & * & stostore re in in an an arrarray ay untuntil il # co# comesmes.... 11

11.. If If ththe are arraray sy sizize ie is bs belelow ow 2525, t, thehen it n it is is a vaa valilid med messssagagee 1

122.. TThhe e 11stst_{6 characters in the array is the}_{6 characters in the array is the password.}_password. 13

13.. FoFollllowowining tg the he papasssswoword rd is is ththe e cocommmmanand.d.

Deleting the SMS: Deleting the SMS:

1

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2 2.. DDeellaay y 1 1 mmsseecc.. 3 3.. SSeennd d SSMMS S nnuummbbeerr.. 4 4.. SSeennd d 00xx00DD.. 5 5.. SSeennd d 00xx00AA.. 6.

6. KeKeep ep on on rerececeivivining chg chararacacteters rs frfrom om ththe me mododem em titill ll ‘K‘K’ c’ comomeses.. 7

7.. WWhehen ‘n ‘K’ K’ iis s rreecceeiivveded, S, SMMS S iis s ddeelleetteedd..

Sending status to user:

1

1.. SSeennd d ““AATT++CCMMGGSS==”” 2

2.. SSeennd d tthhe e sseennddeerr’’s s pphhoonne e nnuummbbeerr.. 3

4.. SSeennd d tthhe e mmeessssaagge e tto o bbe e sseenntt.. 5

5.. SSeennd d 00xx11AA..

3.6.6 GSM COMMANDS

This document describes the

This document describes the AT-comAT-command based mand based messamessages exchanged ges exchanged betwebetweenen an application and the products in order to manage GSM related events or services. To an application and the products in order to manage GSM related events or services. To check the modem whether it is functioned or not by using command, AT cmd - Enter the check the modem whether it is functioned or not by using command, AT cmd - Enter the AT in hyper terminal or in serial port, the

AT in hyper terminal or in serial port, the modem will responses as OK.modem will responses as OK.

To check whether the SIM is there

To check whether the SIM is there or not there in the modem,or not there in the modem,

AT + CPIN? -> Modem responses as “CPIN READY” or “+CME ERROR” AT + CPIN? -> Modem responses as “CPIN READY” or “+CME ERROR” Some commands are

Some commands are

1.

1. Call Control commands:Call Control commands:

The ATD command is used to set a voice, data or fax call. The ATD command is used to set a voice, data or fax call. ATD<nb>; enter where nb is the destination phone number ATD<nb>; enter where nb is the destination phone number Ex: ATD+919845598455; -> Voice call

Ex: ATD+919845598455; -> Voice call Modem Responses –> OK or BUSY or NO

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2. Hang-Up Command: 2. Hang-Up Command:

The ATH command is used

The ATH command is used by the application to disconnect the remote by the application to disconnect the remote user.user. ATH - > modem responses as OK,

ATH - > modem responses as OK,

3. Answer a call: 3. Answer a call:

ATA

ATA - > to- > to answering the incoming callanswering the incoming call,,modem responses as OK.modem responses as OK.

4. Redial last telephone number 4. Redial last telephone number::

ATDL -> Redial the last number for ex, last number is 9845598455, then modem ATDL -> Redial the last number for ex, last number is 9845598455, then modem will dial the number automatically.

will dial the number automatically.

5. Automatic answer ATS0 5. Automatic answer ATS0

This ATS0 parameter determines and controls the product automatic answering This ATS0 parameter determines and controls the product automatic answering mode.

mode.

6.

6. Short message commandsShort message commands

New message indication +CNMI New message indication +CNMI

This command selects the procedure for message

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7. Read message: 7. Read message:

This command allows the application to read stored messages. This command allows the application to read stored messages.

AT+CMGR = 1 - > to read the message modem responses +CMGR : “REC AT+CMGR = 1 - > to read the message modem responses +CMGR : “REC UNREAD”,<phone number>,<date>,<time> ,<enter>

UNREAD”,<phone number>,<date>,<time> ,<enter>

8. List message +CMGL 8. List message +CMGL

This command allows the application to read stored messages, by indicating the This command allows the application to read stored messages, by indicating the type of the message to read.

type of the message to read. AT + CMGL

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9. Send message +CMGS 9. Send message +CMGS

AT+CMGS=”<address>”, <enter>, <message>, <ctrl-Z> AT+CMGS=”<address>”, <enter>, <message>, <ctrl-Z>

The <address> field is the address of the terminal to which the message is sent. The <address> field is the address of the terminal to which the message is sent. To send the message, simply type, <ctrl-Z> character (ASCII 26). The text can To send the message, simply type, <ctrl-Z> character (ASCII 26). The text can con

contaitain n all all exiexististing ng charcharactacters ers exceexcept pt <ct<ctrlrl-Z> -Z> and and <ES<ESC> C> (AS(ASCII CII 27)27). . ThiThiss command can be aborted using the <ESC> character when entering text.

command can be aborted using the <ESC> character when entering text.

10. Delete message +CMGD 10. Delete message +CMGD

This command is used to delete one or several messages from preferred message This command is used to delete one or several messages from preferred message storage.