Architecture and power
Power Networks: A Novel Neural Architecture to Predict Power Relations
... social power relations that exist between participants of an interaction? Prior work within NLP has shown promise in this area, but the performance of automatically predicting power relations using NLP ...
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RF low power subsampling architecture for wireless communication applications
... low power radio frequency (RF) transmission devices, especially the RF ...low power subsampling architecture for wireless communication applications is proposed in this ...subsampling ...
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DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test
... of power switches must consider a distributed model for the PDNs in order to avoid fault coverage loss and yield ...DFT architecture (Figure 11), which is suitable for both ring and grid power gating ...
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On chip communication architecture power estimation in high frequency high power model
... communication architecture solved the problem of how to interconnect hundreds of processing element (PE) and storage element (SE) inside one chip, but in the other hand it introduced power consumption ...
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A POWER EFFICIENT AND ENHANCED VLSI ARCHITECTURE FOR VEDIC MULTIPLIER
... Square Architecture Based On Ancient Indian Vedic Mathematics”, Proceedings of the 2004 International Conference on [6] Sri BharatiKrisna,Tirthaji Maharaja, Jagadguru Swami, “Vedic Mathematics or Sixteen Simple ...
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A Dynamic Filter Architecture for Low Power Consumption
... reducing power consumption of FIR filter generally focus on the optimization of the filter coefficients while maintaining a fixed filter order ...filter architecture is decided, the coefficients cannot be ...
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Design of Low Power NATURE Architecture by Using SRAM
... low power at standby mode also its cost is low at design ...NATURE architecture based on the ...low power for performing the read and write operation compare with other logic ...
5
A Novel UPQC Architecture for Power Quality Control
... the power of the series unit, given the maximum current ...the power factor of load is between ...distribution power losses should be estimated, in order to understand the energy cost associated with ...
5
Low Power Parallel VLSI Architecture for Mbist
... The SoC Interface is an important part of the overall BIST architecture because it will determine whether BIST integration, verification and programming will be easy or cumbersome. Many solutions propose a serial ...
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Area and power efficient DCT architecture for image compression
... and power consumption. Numerous architectures have proposed a low power, high speed and area efficient hardware implementation for DCT computa- tion ...
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A Review on Architecture of Low Power VLSI Design
... systems, power-flow was a secondary-activity and all are considering that as a secondary-terminology as well as give more concentration on compatibility, goodput and ...and power-wise simpler designing with ...
5
Low Power Architecture For Cochlear Implant
... The ARM7TDMI core is the core of the chip and is responsible for the processing of the incoming sound. It converts the sound samples into stimulation commands for the implant, according to the programmed stimulation ...
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Power Efficient Survivor Memory Architecture for Viterbi Decoder
... which power and decoding latency are ...(RE) architecture has the lowest dec odi ng lat e nc y L ...high power consumption. In this paper, we propose a new SMU architecture which combines the ...
7
Novel low power CAM architecture
... proposed architecture significantly reduced the overall static current by almost 100 ...dynamic power dissipation is also reduced. The total dynamic power dissipated in the Traditional CAM ...
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VLSI Implementation of LiCi Cipher
... serial architecture, a reduced datapath architecture and a pipelined architecture are ...serial architecture is based on low area and power with serial processing of the input plaintext ...
8
Monitoring and Controlling Power using Zigbee Communication
... monitoring architecture is used in smart grid to save ...low power-consuming communication technology for coverage area surrounded by 200m, with a data rate ranging from 20Kbps to 250Kbps, it is appropriate ...
5
Mitigating Differential Power Analysis Attacks on AES using NeuroMemristive Hardware
... Artificial neural networks are biologically inspired designs that are capable of doing com- putation in a unique way. Traditionally computers are designed using the Von-Neumann architecture which has registers, a ...
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Trends, Opportunities and Challenges of Emerging Memory Technologies
... leakage power for SRAM and DRAM and the increasing refresh dynamic power for DRAM have posed challenges to circuit and architecture designers of future memory hierarchy designs Emerging memory ...
8
An Efficient, Low Power 256X8 T-SRAM Architecture
... High-speed lookup operations are performed by Ternary Content addressable memories. But TCAMs are limited due to low storage density, relatively access time, low scalability, complex circuitry, and are very expensive in ...
5
Synthesization of Low Power Digital Signal Processor Architecture
... the power as well as energy is ...limited power and ...tree architecture is proposed to send the data in the way of wireless communication ...
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