• No results found

bus architecture

Performance evaluation of a process bus architecture in a zone substation based on IEC 61850-9-2

Performance evaluation of a process bus architecture in a zone substation based on IEC 61850-9-2

... process bus system with multi-vendor devices and operating in IEC 61850-9-2 ...process bus architecture in terms of reliability in protection, distribution of process intelligence, and interface ...

5

NOC AND BUS ARCHITECTURE: A COMPARISON

NOC AND BUS ARCHITECTURE: A COMPARISON

... In the NoC architecture, there are several techniques for power management that are difficult to implement with traditional busses. The NoC can be divided into sub-networks .In any specific application if any ...

5

Develop process bus architecture for integrating sampled
value IEDs

Develop process bus architecture for integrating sampled value IEDs

... ultimate architecture required for a two by 32MVA transformer substation ...ultimate architecture. These were scalability of the structure of the process bus and the physical connection arrangement ...

130

A Distributed Network Switch Bus Architecture for Small Satellites.

A Distributed Network Switch Bus Architecture for Small Satellites.

... data bus was time consuming, complicated and had a significant need for redesign for each mission, which indeed increased the design cost in delivering each spacecraft to ...centralized architecture to a ...

72

Reliability-aware multi-segmented bus architecture for photonic networks-on-chip

Reliability-aware multi-segmented bus architecture for photonic networks-on-chip

... non-blocking architecture allows the system to avoid congestion around the hotspot core, causing the energy per message to remain lower than with transpose ...

45

Design of an AMBA AHB Reconfigurable
Arbiter for On-chip Bus Architecture

Design of an AMBA AHB Reconfigurable Arbiter for On-chip Bus Architecture

... AHB Bus. Before starting the AMBA AHB transfer, the bus master must have to be granted access to the ...the bus. This decision of granting the access to bus is achieved using some arbitration ...

8

Design and Implementation of High Performance AHB Arbiter for on chip Bus Architecture

Design and Implementation of High Performance AHB Arbiter for on chip Bus Architecture

... chip bus is an established, open specification that serves as a framework for System- on-chip (SoC) ...performance bus (AHB) and the Advance peripheral Bus ...

10

FPGA Implementation of High Speed AMBA Bus Architecture for Image Transmission and Face Detection

FPGA Implementation of High Speed AMBA Bus Architecture for Image Transmission and Face Detection

... Architecture which is chiefly utilized for information synchronization between various sensors and additionally actuators and primary handling units. Typically the working pace of primary handling unit is ...

7

Use of Black-Bus Architecture in Router Optimization

Use of Black-Bus Architecture in Router Optimization

... Figure 3 shows an example of FIFO queued Black-Bus router structure. Assuming two-dimensional mesh in Figure 3, it has five I/O ports, where four of them are connected to neighboring routers, and the remaining one ...

5

Optimization And Development Of A Low Power Microcontroller For IoT Application

Optimization And Development Of A Low Power Microcontroller For IoT Application

... Microcontroller Bus Architecture (AMBA), I2C bus and clock gating technique are discussed in related to the project of developing low power microcontroller for IoT ...

24

On chip communication architecture power estimation in high frequency 
		high power model

On chip communication architecture power estimation in high frequency high power model

... ARM Bus Architecture (AMBA chip), and that by decomposing the SoC chip power to the power consumed in the logic element such as arbiter, decoder, input devices and output ...the bus wire by using a ...

6

Design of Wishbone Point to Point Architecture and Comparison with Shared Bus

Design of Wishbone Point to Point Architecture and Comparison with Shared Bus

... interface bus protocol is required to increase the productivity with design time ...Chip bus architecture, connecting IP cores together and alleviating System on Chip integration ...

6

TLM based AMBA AXI4 protocol implementation using verilog with UVM environment

TLM based AMBA AXI4 protocol implementation using verilog with UVM environment

... [5]. M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, and C.Turchetti. ”Transaction-level models for AMBA bus architecture usingSystemC 2.0.” Proc. IEEE Conf. Design, Automation and Test in ...

6

Bus Tracking System using IoT

Bus Tracking System using IoT

... college bus tracking system and this application enables the user to find out the bus location information so that user does not get ...and bus real time location can be viewed on google map which is ...

7

Bus Shelters as Shared Public and Private Entities; and Bus Shelter Advertising Contracts (BSACs), a Product and Source of Global Change: an Overview, History, and Comparison

Bus Shelters as Shared Public and Private Entities; and Bus Shelter Advertising Contracts (BSACs), a Product and Source of Global Change: an Overview, History, and Comparison

... of bus shelters has received perhaps the most press, as well as been the subject of the most academic query, in Los ...year-old bus shelter system, which during that period underwent several questionable ...

59

Design analysis of 132/33 kv grid substation fazilpur, dist  sonepat, Haryana

Design analysis of 132/33 kv grid substation fazilpur, dist sonepat, Haryana

... Bus bars are Cu/Al rods of thin walled tubes and operate at constant voltage. The bus-bars are designed to carry normal current continuously. The cross section of conductors is designed on the basis of ...

8

EK DQ11 MM 002 DQ11 NPR Synchronous Line Interface Manual Apr75 pdf

EK DQ11 MM 002 DQ11 NPR Synchronous Line Interface Manual Apr75 pdf

... Sample Message Wit.'1 Received Data Character and VRC Block Diagram of Receive Character Control Logic Block Diagram of AB Bus Selectors and Decoding Logic Block Diagram of Architecture [r] ...

230

[0201699567]Real Time Design Patterns pdf

[0201699567]Real Time Design Patterns pdf

... solutions. Architecture is a part of design because there are many designs that could be used to implement an analysis model, so it is not, in that sense, ...good architecture is at least approximately ...

342

DC Power Balance during Charging of Electric Vehicles

DC Power Balance during Charging of Electric Vehicles

... The comprehensive DC power balance management principle for the fast charging of electric vehicle is proposed with bipolar DC bus. This fast charger has the dc power balance capability and eliminates the use of ...

8

Multi channel multi clock frequency speed rate real time industrial standard parallel prbs cdma transceiver array asic soc card design for ultra high speed wireless communication products/application cards

Multi channel multi clock frequency speed rate real time industrial standard parallel prbs cdma transceiver array asic soc card design for ultra high speed wireless communication products/application cards

... Design Architecture and Implementation of Multi clock frequency tech PRBS CDMA Transceiver Bus Array me Industrial Communication Interface Cards/Products like Data Acquisition and Tracking of wireless Data ...

8

Show all 9751 documents...

Related subjects