IEEE-754 double-precision format
Design of High Speed Single Precision Floating Point Multiplier Using Vedic Mathematics
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FPGA based High Speed Double Precision Floating Point Divider
6
Design and Implementation of Floating Point Complex number Multiplier Using Modified Vedic Algorithm
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Design and Analysis of Matrix Multiplication using IEEE 754 Floating Point Multiplier Partition Technique
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Survey of Matrix Multiplication using IEEE 754 Floating Point for Digital Image Compression
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VLSI Implementation of Neural Network
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Implementation of 32 bit Floating Point Multiplier and Adder for FFT Processor Using VHDL
6
Resilient Iterative Linear Solvers Running Through Errors.
169
An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm
6
Design and Simulation of Floating Point FFT Processor Based on Radix-4 Algorithm Using VHDL
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High Speed IEEE 754 Floating Point Multiplier using Different Types of Adder
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Asymptotics and Well Posedness of the Derived Distribution Density in a Study of Biovariability
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Combining Secret Sharing and Garbled Circuits for Efficient Private IEEE 754 Floating-Point Computations
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Nevada FORTRAN Ver 3 0 Jun83 pdf
225
Ieee Format For Thesis Writing >>>CLICK HERE<<<
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Design and Implementation of IEEE 754 Addition and Subtraction for Floating Point Arithmetic Logic Unit
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Trans-Floating-Point Arithmetic Removes Nine Quadrillion Redundancies From 64-bit IEEE 754 Floating-Point Arithmetic
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A Double Auction Market with Signals of Varying Precision
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19771107 Memo327 FORTRAN S Language Revised pdf
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Computing Centre Newsletter No. 42, June 1980
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