IEEE Floating Point Formats
Multiplication using IEEE 754 Floating Point for Image Compression
5
Trans-Floating-Point Arithmetic Removes Nine Quadrillion Redundancies From 64-bit IEEE 754 Floating-Point Arithmetic
6
Review Paper on Matrix Multiplication using IEEE 754 Floating Point and Different Types of
5
Survey of Matrix Multiplication using IEEE 754 Floating Point for Digital Image Compression
8
Optimized Design and Implementation of Ieee-seventy hundred fifty-four Floating Point Processor
5
High Speed IEEE 754 Floating Point Multiplier using Different Types of Adder
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Design and Analysis of Matrix Multiplication using IEEE 754 Floating Point Multiplier Partition Technique
8
Design of Floating Point Adder/Subtractor and Floating Point Multiplier for FFT Architecture Using VHDL
8
The pitfalls of verifying floating-point computations
41
Inexact Floating Point Adders Analysis
6
IEEE 754 compliant floating point fused add sub unit
5
Precision & Performance: Floating Point and IEEE 754 Compliance for NVIDIA GPUs
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IEEE 754 Single Precision Floating Point Arithmetic Unit Using VHDL
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Design and Implementation of IEEE 754 Addition and Subtraction for Floating Point Arithmetic Logic Unit
7
Verifying a Synthesized Implementation of IEEE-754 Floating-Point Exponential Function using HOL
40
Double Security Watermarking Algorithm for 3D Model using IEEE 754 Floating Point Arithmetic
5
Combining Secret Sharing and Garbled Circuits for Efficient Private IEEE 754 Floating-Point Computations
20
Floating Point Instructions
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Automatic Floating-Point to Fixed-Point Transformations
5
Basics of Floating-Point Quantization
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