low on-chip power consumption
Effective Routing Algorithm and Topology on Power Consumption in Networks on Chip
... about power reduction with using low power encoding should be ...the power improvement is better when the links power dissipation is ...of low power encoding techniques on ...
8
IOT Based ECG Monitoring For Smart Healthcare
... ABSTRACT: Many researches are done for monitoring ECG for Health dieses analysis. Proposed system is design to monitor Health using TEMPERTURE SENSOR, mixed-signal ECG System-on-Chip (SoC) with ...
5
Ultra Low Power Consumption Military Communication Systems
... New military communications require increased versatility for the transmission of a wide range of data, voice and images. There are many algorithms needed for communication like FFT (Fast Fourier Transform), DCT ...
6
A Scalable & Energy Efficient Graphene-Based Interconnection Framework for Intra and Inter-Chip Wireless Communication in Terahertz Band
... of power consumption and the area overhead ...enables low area overheads by using these antenna arrays enabling the use of multiple antenna arrays in each ...
73
A Systematic Technical Survey Of Lightweight Cryptography On Iot Environment
... minimize power consumption in hardware and software implementations and to minimize power consumption that is required to keep memory and ...for low-cost devices. The power ...
16
Design of Efficient Router with Low Power and Low Latency for Network on Chip
... of Chip (NoC), which aims at obtaining low latency and low power consumption by concerning wired and wireless links between ...and power consumption of the network on ...
11
Fall Detection Application on an ARM and FPGA Heterogeneous Computing Platform
... the power consumption, execution time for implementing the Fall Detection application but also takes the advantage of Open source Computer Vision (OpenCV) ...real power consumption, estimated ...
9
Design of Low-Power Full Adder Using GDI Structure and Hybrid CMOS Logic Style
... save chip area [1, 2, 3, 4, ...save chip area does have excellent performance, however, due to MOS transistors reduced, these full adders have threshold voltage loss problem and poor output driving ...
10
Design of a LNA in the frequency band 1.8–2.2 GHz in 0.13 m CMOS Technology
... a low noise amplifier (LNA), operating in the frequency range ...the low cost of the final ...reason low power consumption is taken into consideration (low supply voltage and ...
5
Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On Chip Instruction Cache
... for low-energy microcontrollers have been increasing in recent ...large power consumption required in accessing an NV memory has become a major ...the power supply voltage of NV ...
13
Energy Efficient Virtual Machines Placement in IP over WDM Networks
... In [3], the authors designed a framework to evaluate the power consumption of cloud services in IP over WDM networks. They developed a Mixed Integer Linear Programming (MILP) model to consider three clouds ...
5
Power and area efficient modified booth multiplier for low power consumption
... Lei Wang (2003), briefly describes the A low- power technique for digital filtering referred to as adaptive error-cancellation (AEC) is presented. The AEC technique falls under the general class of ...
9
LOW POWER AND HIGH PERFORMANCE SERIAL COMMUNICATION INTERFACES FOR ON-CHIP INTERCONNECTS
... tolerable frequency differences. In the first method, a strobe line was used to activate the oscillators. Local counters were used to count the number of bits in the data frame and to stop the local oscillators when the ...
19
Volume 2, Issue 7, July 2013 Page 119
... An online GPRS-Sensors Array for air pollution monitoring has been designed, implemented, and tested [8]. Theproposed system consists of a Mobile Data-Acquisition Unit (Mobile-DAQ) and a fixed Internet-Enabled Pollution ...
6
Low Power Decimator Design Using Bit-Serial Architecture for Biomedical Applications
... In [7], several bit-serial architectures are proposed. The basic block diagram for the decimator in [7], as seen in Fig. 4, is an adder with a 25-bit shift register for the integrator section and another 25-bit shift ...
5
Low Area 8 Bit Multiplier using Hardware Reuse Technique
... In section III we have discussed simple array multiplier, we need to cut down the area requirement of the multiplier, there are many possibilities one of them is using low power adder. In this design we ...
6
A Dynamic Filter Architecture for Low Power Consumption
... error power ratio or the SNR of a given system, which are usually less than 30 dB [12], the performance degradation of proposed reconfigurable FIR filter can be considered ...amplitudes.. Power saving ratio ...
7
3D printed components for quantum devices
... sen to be small for reasons of power consumption while still being large enough to permit laser beams with sufficient diameter to enter the central trapping region. We include electric feeds that ...
9
Design and Implementation of Energy Efficient Environment Monitoring System
... with power management technique. In this power management technique that is duty cycling with changing the sampling interval is proposed to reduce the power consumption of sensors and ...
7
Investigate the possibility of using carbon onion nanolubrication with DLC cutting tool to reduce the machining power consumption
... rapid consumption of world's fossil fuel resources and impracticality of large-scale application and production of renewable energy, the significance of energy efficiency improvement of current available energy ...
6