[PDF] Top 20 WRL TN 16 pdf

... Several trace-based studies have analyzed cache performance under multiprogramming workloads. When true multiprogramming traces have not been available, as in Smith [16] and in Thiebaut and Stone [18], single ... See full document

... Our first result assumes that we score candidate profiles by the specific matching criterion, for n = 1, 2, 4, 8, 16, 32, 64, and 128. Given a test program and a value of n, we proceeded as follows. An estimated ... See full document

... Figure 7 compares three-category attribute caches having large ID and sequential subcaches against the baseline cache, and against a two-category cache having 16-Kbyte blocks in its general I/O subcache. The ... See full document

... The last five columns in this table indicate how well the cross-validation profile can predict the outcome of the conditional branches in libc. The column labeled “BTFNT” represents the conditional branch miss rates ... See full document

... are actually providing an effective line size that varies on a per reference basis within each program. Also note that the line size used in the stream buffer approaches is not that significant, although it is very ... See full document

... hardware reset). When the Itsy computer must boot from the daughter-card, this signal should never be set to 0 during sleep mode, since the processor would be unable to read the boot memory upon wake up. This can be ... See full document

... Other forms of optimization depend on having the entire program at hand all at once. In an environment with separately-compiled modules, this may mean we must apply the optimization to machine-level code. Global ... See full document

... While this allows higher bandwidths to be sustained, it increases the overall latency and so is not acceptable in logic circuits. Figure 6 plots the bandwidth vs. latency vs. speed-power product of implementing various ... See full document

... The Dictation experiment, a continuous speech recognizer, really stretches the Itsy’s capabilities. Be- cause the recognizer runs about 2.4 times slower than real time, and the battery lasts only 2.8 h, an Itsy can only ... See full document

... caches. For caches of this size access times of 16 to 30ns are likely. This yields an access time for the cache of 4 to 30 instruction times. The relative speed of the processor as compared to the access time of ... See full document

... The color server uses assembly code to implement the above algorithm. Coding in assembler allows optimizations that even a very good compiler and code scheduler would probably miss. In the assembly language version, all ... See full document

... As expected, the power consumption during sleep mode has significantly improved on Itsy v2.4 with respect to Itsy v2.3 [Vir00], while the power consumption during idle and run modes remained essentially the same. This is ... See full document

... The last column in Table 5 is a relative figure showing how well each configuration can move large uncached blocks of memory relative to how fast it executes normal instructions. I com- puted this figure by taking the ... See full document

... The author is also indebted to the Itsy team at the Western Research Laboratory (WRL) and System Research Center (SRC): Joel Bartlett, Lawrence Brakmo, David Chaiken, Je Dean, Puneet Kumar, Bob Mayo, Sharon Perl, ... See full document

... A new version of the WRL tracing facilities collected the traces on DECstation 5000’s running UL- TRIX [3, 4]. Its kernel-based approach traces all processes. Figure 1 shows the system configuration. The original ... See full document

... We want our IIS systems to handle as high a request rate as possible, but when that rate is exceeded, we do not want them to suffer from congestive collapse or ‘‘livelock.’’ A livelocked[r] ... See full document

... This work would not have been possible without the skills and interest of my colleagues at WRL: William Hamburgen, Marc Viredaz, Wayne Mack, Deborah A. Wallach, Lawrence Brakmo, and Andreas Nowatzyk. Stu- dio Red ... See full document

... at WRL ranges from Web search engines to tools to optimize binary codes, from hard- ware and software mechanisms to support scalable shared memory paradigms to graphics VLSI ...of WRL tradition, we test our ... See full document

... We do work in the design, fabrication and packaging of hardware; language processing and scaling issues in system software design; and the exploration of new applications areas that are opening up with the advent of ... See full document

... When Mom simulated the CMOS inverter ring using the switched-resistor models 68% of the execution time was spent in timing analysis and 18% of the time was spent rescheduling transistors[r] ... See full document