At this point, a number of tests were conducted to evaluate the performance of the SGA system when compared with other optimisation algorithms. The comparisons were made using using the MOTIVATED system with the same circuit test-bench, SPICE parameters and objectives as given in the previous set of tests. Variability was not considered in these tests due to the time taken to run variability-aware experiments on a single workstation, so the comparative tests were based on the optimisation of circuits for power and delay using uniform models only, and are compared with the results at the end of the uniform-stage in the previous sets of experiments. It is acknowledged that this is undesirable as other optimisation algorithms may indeed perform well at the variability stage. Only two test circuits from the VSCLIB were used in the comparison tests: firstly the NAND gate, and secondly the XOR gate.
5.3.1 Steepest-Ascent Hill Climbing
The first set of tests was based on a steepest-ascent hill climbing algorithm. To allow this algorithm to be used with the current MOTIVATED system, it was implemented as a adap- tation of the mutation operation within the SGA framework. To allow this, the population at each generation consists of µ parent and λ offspring, where mu is set to the number of
objectives2 and where λ is 2× the number of genes within the genotype. In the replaced mutation operation, each of the offspring has one gene adjusted a single unit up or down from the parent’s value respectively, such that all λ offspring represent the entire set of possible so- lutions with one transistor value shifted. These are then assessed by SPICE and ranked using the multi-objective fitness function, using the same method as before, with the highest ranked individuals being promoted to the next generation. A memory of previously visited circuits is stored, with the algorithm terminated once a generation in which all of the new individuals have previously been assessed is found.
The algorithm was used with two test circuits: the NAND gate and the XOR gate from the VSCLIB, as used in the previous experiment and illustrated in Figure 5.5. For the first test, the algorithm was launched with an initial population in which every NMOS transistor was set to 4-units of width (140nm) and every PMOS transistor was set to 8-units of width (280nm)3. For the NAND gate circuit, the algorithm terminated after 19 generations. The six parents from the final population were all found in the final population of the equivalent run in the SGA algorithm: for this circuit, the SAHC had proven far more efficient. However, for the XOR circuit, the algorithm terminated after 42 generations, and the extracted parents from the final population were less effective that those found in the SGA run in all objective scores with the exception of circuit area. These results indicate that the landscape for the NAND gate circuit is relatively smooth, despite the number of dimensions, thus very suited to the SAHC algorithm; in contrast the landscape for the XOR circuit clearly contains many local optima.
5.3.2 SAHC With Random Walk
The SAHC algorithm was adapted so that it both began with a randomised population, and so that in each generation an extra randomised parent circuit was included in the population, to add a periodical random walk to the algorithm. The algorithm was once again applied to the NAND and XOR circuits, although this time 5 runs for each test were carried out, with the algorithms terminated after 357 generations for the NAND circuit and 848 generations for the XOR circuit; these values were chosen so that an equivalent numbers of circuits would have been assessed in both the SAHC run and the SGA run described previously.
As expected, in all five runs for the NAND gate circuit, results were found which matched those from the SGA algorithm, confirming that both the extracted results are indeed the best that can be acheived for the given objective scores, and also that the underlying shape of the search space for the NAND circuit is devoid of many local optima. For the XOR circuit,
2
Excluding the functionality objective
3
there were significant differences observed across the five runs, with the best observed results across all the SAHC algorithm runs producing better results than the SGA in certain fitness objectives (area and σ delay), and worse in others (power). Given both were given a similar length of circuit evaluations, it is hard to determine categorically which is the more efficient, although the results do suggest that the SGA may be more effective in larger circuits, with more complex fitness landscapes, whilst the SAHC clearly outperforms it in smaller circuits with simple landscapes. A detailed comparison of all the results between the SGA, the SAHC and the SAHC with random walk can be found in Table A.3 within Appendix A.