A final set of experiments carried out using the MOTIVATED system prior to SGE-cluster
implementation being created involved optimising the transistor widths in designs that had previously been evolved using CGP.
5.5.1 Using CGP To Evolve Standard-Cell Topologies
As part of his research in the nano-CMOS project, Dr. James Walker has devised a system for evolving standard-cell topologies, based on an adapted representation of previous work he had conducted in Cartesian Genetic Programming, as previously discussed in Section 4.1.2. As a result of this work, two novel topologies for XOR and XNOR gates had been extracted. Using the same methodology and settings described in Section 5.2, the optimisation process was applied to the new topologies to see how they performed in terms of power, speed and variability tolerance.
5.5.2 Evolved Designs
The best designs that were extracted from the CGP runs are illustrated in Figure 5.16. The evolved XOR design uses 10 transistors, and the evolved XNOR uses 8 transistors. Both of the evolved designs are structurally and characteristically similar to conventional CMOS designs, however differ from any designs found in the VSCLIB and NANGATE cell-libraries, and are considered as fair as the public-domain literature is available to be novel in their topologies. During the CGP evolution process within MOTIVATED all the transistors within
(a) (b)
Figure 5.16: CGP-evolved designs for the XOR gate (a) and the XNOR gate (b).
the circuits were given static width dimensions of 5-units for NMOS (175nm) and 10-units for PMOS (350nm). The goals of the optimisation process using the SGA was to optimise these dimensions to extract circuits which improved performance in terms of delay, power and variability tolerance. The template netlists for these circuits used by the SGA can be found in Appendix C.1.4.
5.5.3 Results
The MOTIVATED system was used with the SGA to optimise the two evolved circuits with uniform models, using exactly the same parameters as in the previous runs on the VSCLIB described in 5.2 in order that the two sets of results can be directly compared. A comparison of the initial and final populations at the end of the uniform stage of the evolutionary run are shown in 5.17. For both circuits a marked improvement in the best power and delay scores can be seen when compared to the unoptimised design (with all NMOS transistors at 5 units wide and all PMOS transistors at 10 units wide); however, when compared directly to the VSCLIB results from Figure 5.7, the pareto fronts are less defined with a greater scattering in the output, particularly in the case of the XOR design. The algorithm was then restarted using the variability models as before. At the end of this run, three circuits were extracted: a high-speed design (HS), a design balanced between high-speed and low-power (SP) and a low-power design (LP).
5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 100 120 140 160 180 200 220 240 260 Vdd Power Worst Delay (pS) Generation 0 Generation 1000 Unoptimised (a) 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 120 140 160 180 200 220 240 260 280 300 Vdd Power Worst Delay (pS) Generation 0 Generation 1000 Unoptimised (b)
Figure 5.17: The worst case delay and power statistics of the population at the initial genera- tion and after the uniform-stage of optimisation for the CGP-evolved XOR (a) and XNOR (b) standard cell designs.
based on the SCL designs in Table A.5, found in Appendix A. Although the optimised evolved designs for the XOR and XNOR are much slower than the SCL designs, they are also signif- icantly lower in power consumption, and are smaller in transistor area (this is not surprising for the evolved XNOR, as it contains one fewer MOSFET than the SCL design, so it natu- rally has an advantage). The effects of variability on the worst-case delay scores and power scores for both the SCL designs and the CGP-evolved designs are compared in Figure 5.18. The optimised VSCLIB SCL designs show less variability than the CGP evolved designs, both terms of power and delay. However, this is partly a consequence of the VSCLIB designs being larger and consuming more power, both of which have been shown to reduce the effects of variability [22].
The range of delays across the variability runs is far greater in the CGP evolved designs than the SCL designs; at the greatest extreme, the low-power evolved XOR design ranged between 190 pS and 322 pS delay across RandomSPICE circuits, which is in stark contrast to the range of 80 pS to 86 pS delay observed for the high-speed VSCLIB design. These experiments thus revealed that whilst the CGP-evolved designs offered benefits over the SCL designs if low-power circuits are required, they performed poorly when variability was consid- ered, whilst the conventional designs actually demonstrated a far better degree of variability- tolerance. This does, however, emphasise both the importance that topology choices have in created variability-tolerant designs, and the sacrifices in terms of delay-variability that have to be made when low-power cells are needed.
15 20 25 30 35 40 50 100 150 200 250 Power Score (x1000) Worst Delay (pS) HS-XOR - Var HS-XOR - Uni SP-XOR - Var SP-XOR - Uni LP-XOR - Var LP-XOR - Uni
(a) VSCLIB XOR
15 20 25 30 35 40 50 100 150 200 250 Power Score (x1000) Worst Delay (pS) HS-XNOR - Var HS-XNOR - Uni SP-XNOR - Var SP-XNOR - Uni LP-XNOR - Var LP-XNOR - Uni (b) VSCLIB XNOR 0 5 10 15 20 25 100 150 200 250 300 Power Score (x1000) Worst Delay (pS) HS-XOR - Var HS-XOR - Uni SP-XOR - Var SP-XOR - Uni LP-XOR - Var LP-XOR - Uni (c) CGP-Evolved XOR 0 5 10 15 20 25 100 150 200 250 300 Power Score (x1000) Worst Delay (pS) HS-XNOR - Var HS-XNOR - Uni SP-XNOR - Var SP-XNOR - Uni LP-XNOR - Var LP-XNOR - Uni (d) CGP-Evolved XNOR
Figure 5.18: Comparison of the impact of RDD variability on the worst-case delay and power statistics between the conventional VSCLIB designs (top row) and the CGP evolved designs (bottom row) for the high-speed, balanced and low-power XOR and XNOR gate extractions.