Random Dopant Placement

Traditionally, transistor models have been based on assumptions of statistical averaging of the dopant concentrations, which results in smooth carrier concentration and potential profiles. This assumption is valid provided the number of dopants, and their specific position within the device, result in negligible differences between devices. However as devices scale well into the sub-100nm lengths, the number of dopant atoms within the active region of a device is relatively low. This results in devices which exhibit behaviour determined by the actual number and specific placement of dopant atoms; certain parts the device will become active before others, leading to a lower average threshold voltage than would be anticipated with a continuously doped device. Furthermore, significant variations of threshold voltage will be seen between individual devices on an intra-chip level, with the possibility of neighbouring devices exhibiting a substantial range of threshold voltages [138].

Where the dopants are considered on a per-atom basis with stochastic placement, these are named Random Discrete Dopants (RDD). Random dopants occur due to fabrication processes of modern MOSFET devices. The dopants atoms are implanted into the silicon at very high energies which leads to a scattering process; thermal annealing then allows implanted atoms to replace silicon atoms within the crystal lattice, a process which diffuses their position fur- ther. The nature of these processes mean it is impossible to precisely control the quantity and positions of the individual dopant atoms; every device will have its own unique distribution of dopants and with it a threshold voltage determined by the influence of dopant atoms on the potential. The atomic structures of simulated 22nm and 4nm with random dopants placements are illustrated in Figure 2.9; the 22nm device is representative of minimum sized devices that

(a) 22nm Device (b) 4nm Device

Figure 2.9: The atomic structures of 22nm and 4nm stylized transistors illustrating random discrete dopant placements [22]

will be created within the next five years, whilst the 4nm device, which has less than ten dopant atoms within the active region, is representative of the fundamentally minimum-sized devices that could be fabricated in silicon; beyond this scale it is highly unlikely that satisfactory functional devices could be assembled due to the lack of clearly defined regions.

The potential problem of random dopant placement and is consequences to threshold volt- age variation have been acknowledged for nearly 40 years, being discussed in a 1972 paper by Hoeneisen and Mead, in which it was predicted that once devices reached channel lengths of 150nm, one-in-a-million devices would experience threshold voltage variations in excess of 20% [73]. A further detailed analysis of the effect on threshold and breakdown voltages caused by dopant quantity and placement was given by Keyes in 1975 [81]. The problems of dopant-placement induced variability were then confirmed in experimental observations on actual fabricated devices by Mizuno et al in 1993, in which the VT variability in a fabricated

transistor array with 8,192 devices with channel lengths of Lef f = 0.5µm and Lef f = 0.3µm

was analysed. It was observed that the standard deviation of threshold voltages increased in the devices with smaller channel lengths, confirming that a portion of the overall VT variability

was independent to oxide-thickness variability and instead caused by the stochastic placement of dopant atoms [120, 119]. However it is within the last 10 years that the random dopants have become a real issue for semiconductor designers and manufacturers due to their impact on threshold voltages [144]. The number of dopant atoms present within the channel region a minimum-sized MOS transistor of is now typically around one hundred; in a set of devices simulated by Asenov et al, with effective channel length Lef f = 30nm and channel width

Wef f = 50nm, the number of dopant atoms within the channel depletion followed a Poisson

distribution around a mean value ¯Nd = 130. At this scale and smaller, even assuming a per-

fectly uniform lithography, the randomness of the doping profile leads to significant variation in the actual effective channel length [20].

For contemporary bulk MOSFETs, which continue to be the prevailing design used in the 45- and 32-nm technology generations, random dopants are the dominant source of statistical variability [138]; the contribution of RDD to VT variability has been demonstrated to be within

the 60% to 65% range in fabricated 65- and 45- nm bulk MOSFETs [98]. Alternative technolo- gies such as silicon-on-insulator (SOI) and FinFET devices (a non-planer double-gated design built on a SOI substrate [75]) are able to significantly reduce the impact of RDD variability as they have lower dopant concentrations near the interfaces [19]; such technologies add vast complexity to fabrication, and consequentially increase costs, and are largely reserved for spe- cialist applications at the present time. Besides threshold voltage variations between devices, RDD also impact a number of other major device parameters, such as sub-threshold swing, sub-threshold leakage current and drain current.