The SPICE Circuit Analysis Tool

Circuit simulation programs operate by converting a text-based representation of a circuit, containing component types, values and interconnections (forthwith known as a netlist), then translate this into a set of non-linear differential equations. Depending on the software, these equations are solved using either the Newton-Raphson method, sparse-matrix techniques or implicit integration methods [11]. On of the most widely developed and used bases for circuit simulations is SPICE (“Simulation Program with Integrated Circuit Emphasis” ). It is a well- established design tool and is widely used as a verification tool before designs are committed

C

C

g v

C

v

_g

1

Figure 2.12: Small-Signal Model Equivalent Circuit for a MOS Transistor in Common-Source Configuration, based on illustrations from [160, 48]

to fabrication.

SPICE allows for a number of different types of circuit-analysis to be undertaken. The original version allowed non-linear DC analysis, small-signal steady-state sinusoidal (AC) analysis with noise analysis, and non-linear, time-domain transient analysis. Additional re- visions added DC transfer-curve analysis and transfer-function analysis [128]. Additionally, small-signal analysis of sensitivity, pole-zero and distortion can also be calculated in more recent revisions, along with parametric sweeps to analyse circuits under changing operating conditions [12].

Background and History of SPICE

Computer-aided circuit analysis was first popularised with the Electric Circuit Analysis Pro- gram (ECAP), developed by IBM in the mid-1960’s; this was the first time a system could automatically convert a nodal-description of the circuit into a set of equations and solve them. Subsequent improvements to the ECAP system included SPECTRE, NET, CIRCUS, CAN- CER and TRAC [28]. It is, however, the subsequent SPICE software which has received the most development, which can be attributed to its development at a public university with public-domain availability, and the inclusion of BJT and FET models, resulting in suitability and scalability at simulating both analogue and digital circuits [127].

SPICE is a general purpose analogue circuit simulation tool, originating from the Com- puter Aided Design group of the Electronics Research Laboratory at the University of Califor- nia, Berkeley, in the early 1970’s. The developers who had worked on the proprietary CAN- CER program redeveloped a new public-domain circuit simulator, first presented in 1973. By revising the CANCER code, they removed the proprietary constraints, and importantly added then-advanced device models for the BJT, JFET and MOSFET devices. Given the prevalence

of BJTs in integrated circuits of the time, special emphasis was given to the BJT model in the original SPICE software. However, a key function of the original SPICE software was the possibility of using external device models via .MODEL cards, which would prove to be a key feature in allowing modern devices to be simulated [128].

The original version and its successor SPICE-2 were coded in Fortran-66, and used a process of nodal analysis to solve circuit equations [12]. The original version was tested on a CDC 6400 mainframe computer, with a memory limited to around 140 thousand octal words. This limited the size of circuits that could be simulated in the first version to roughly 50 nodes and 25 bipolar transistors [127]. SPICE-3, the base of the distribution discussed and used in this thesis, was developed in 1989 and is written entirely in C. The original release of Spice- 3 (which shall be considered to be ‘Berkeley SPICE’) contains around 217,000 lines of C source code, spread across 878 separate files. It is regularly used to simulate circuits with several thousand nodes and active devices, generally limited by the memory-footprint of the computer [90].

SPICE functions by analysing the input file to determine all the circuit elements connected to each node, then applying Kirchoff’s current-law to create a set of simultaneous equations for the circuit; the admittance of each branch being the known quantity and the voltages being the unknowns. The equations are formed into an admittance matrix, which is solved using the Newton-Raphson method [28].

Variants of SPICE

Several different packages exist which are based upon the Berkeley SPICE core but add a number of features and enhancements. Some of these are free-to-use, open-source variants, whilst many others are commercial designs. The Berkeley SPICE is limited in its input and output options, working in a ASCII environment; many of the alternatives add features such as interactive alteration of circuits, graphical post-processing and the ability to run on different computing platforms such as personal computers and clusters. Several of the different varieties of SPICE are listed in Table 2.3 [28, 12, 177].

For the work in this thesis, the NGSPICE simulator has been chosen. It is an actively main- tained open-source, free to use variant of SPICE, which works correctly with the variability- aware transistor models that have been created (see section 2.6.1). The lack of licensing restric- tions made it particularly suited to Grid-based evaluation; many of the commercial versions of SPICE, notably HSPICE, have licensing terms which work on a per-installation basis, which places obstacles in the way of a cluster or Grid-based platform where the software is to be distributed across many nodes. Throughout the duration of this thesis a number of revisions of

Table 2.3: Different distributions of SPICE-based Simulation Software

Name Vendor Licence Platform1 _Notes

HSpice R Synopsys R Commercial W,L,S [157]

Multisim National Instruments Commercial W

NGSpice gEDA Project Free (GPL) W,L,M First release 1999 [130]

PSpice R Cadence R Commercial W,L First released 19842[37]

SmartSpice Silvaco Commercial W,L Multithreaded, 64-bit [150]

SpiceOpus University of Ljubljana Free W,L

T-Spice Tanner EDA Commercial W

1

W=Windows, L=Linux, M=Mac/OSX S=Solaris

2_{PSpice is now part of the OrCAD and Allegro toolchains}

Table 2.4: Revisions of NGSPICE used in this thesis

Version Release Date Notes ngspice 17 30-08-2005

ngspice 18 01-12-2008 Allows parametrical netlists, .lib statements

ngspice 19 23-04-2009 Bug fixes in memory management, revised BSim models ngspice 20 16-11-2009 Added .measure statements, updated to BSIM 4.6.5 ngspice 21 21-06-2010 Latest release, updated BSIMSOI model

the NGSPICE software have been released, often adding significant functionality which has improved the operation or performance of the software described in this thesis; generally it has not been possible to repeat all results with the latest version due to the time taken to compute each set of results. A brief synopsis of the NGSPICE versions used is given in Table 2.4.

The BSIM Transistor Model

All variants of SPICE contain different models for field-effect transistors. The original version of SPICE used a model originally proposed by Shichman and Hodges, which is now consid- ered to be the SPICE ‘Level 1’ model. This is a large signal model, which is solved using the formula shown in Equation 2.19, in which µOis the surface mobility of the n-channel device,

Cox is the capacitance per unit area of the gate oxide, W is the effective channel width and L

is the effective channel length [149].

iD = µ0CoxW L h (vGS− VT) − vDS 2 i vDS (2.19)

A small-signal model can be derived from the above equation, which is suitable accurate for large MOSFET devices provided the length and width of the MOS device are greater than

10µm and the substrate doping is low. Once devices approached this size, a far more accurate model was required, which resulted in the development of the SPICE Level-3 model at Berke- ley. This model adds narrow and short-channel effects to the basic large-signal model which requires a number of additional parameters to be considered. These include drain current, threshold voltage, effective carrier mobility, saturation voltage and channel length modula- tion; sub-threshold conduction is also present in the model. Despite containing 19 different parameters the model is not accurate enough to simulate modern devices; it is useful for de- vices down to 0.8µm in size [64].

At geometries below 0.8µm, the standard SPICE models fail to accurate reflect the ob- served characteristics of devices. In 1984, the BSIM1 model was introduced to address the need for a more accurate sub-micron model; the model contained 60 parameters and ap- proached the modelling problem as a multi-parameter curve fitting exercise; whilst some of the parameters were related to device physics, it was largely a non-physical model. In 1991 an updated model, BSIM2, was released, to account for more accurate modelling of output resis- tance changes resulting from source/drain parasitic resistance, inversion-layer capacitance and hot-electron effects. This model upped the parameter count to 99, which results in significant expertise in designing and fitting models to specific devices. In 1994 a third model, BSIM3, was released, which returned the main function of the model to being based on device-physics rather than curve-fitting; as a consequence fewer parameters were needed (40 for BSIM3v2) and improved performance in modelling analogue circuits was observed. The subsequent BSIM3v3 simulation model includes modelling for all the relevant parasitic effects down to 0.15µm channel length devices, using extra parameters and additional values for the capaci- tances and resistances of metal lines to describe an individual transistor. This level of detail led to the BSIM3v3 model becoming the industry standard MOS transistor model [16]. A com- parison of the performance and minimum channel lengths and oxide thickness for different SPICE models is given in Table 2.5.

The most recent series of BSIM models is BSIM4, originally released in the year 2000, which aims to address the physical effects observed in sub-100nm devices. It is essentially an extension of BSIM3, and continues the physics-based approach to modelling. It adds a more accurate model for intrinsic input resistance, a channel thermal-noise model and a gate direct tunnelling for multi-layer gate dielectrics, amongst 24 other total developments over BSIM3v3. The latest revision as of time of writing is BSIM4.6.5, released in September 2009 [124]. Due to the vast number of calculations and models necessary to describe the BSIM3 and BSIM4, they are not included here; they are covered in detail in [18, 64] for the BSIM3 series models and [124] for the BSIM4 series.

Table 2.5: Performance comparison of MOSFET Models available in SPICE [42, 16, 64]

Model Minimum L Minimum Tox Subthreshold Small Signal

(µm) (µm) Accuracy Accuracy

MOS Level 1 5 50 Not modelled Poor

MOS Level 2 2 25 Poor Poor

MOS Level 3 1 20 Poor Poor

BSIM1 0.8 15 Fair Poor

BSIM2 0.35 7.5 Good Fair

BSIM3v2 0.25 5 Good Good

BSIM3v3 0.15 4 Good Good

BSIM3v4 0.13 3 Good Good

BSIM4v6 < 0.09 < 3 Good Good