Duplex Operation

The 82546GB/EB and 82545GM/EM supports half-duplex and full-duplex 10/100 Mb/s mode.

Half-duplex in 1000 Mb/s mode using either the Internal SerDes or GMII interface is NOT supported.

The 82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI, support half-duplex and full-duplex 10/100 Mb/s mode or 1000 MB/s mode. However, only full-duplex mode is supported when the 82544GC/EI TBI interface option is used.

1. MDIO/MDC Interface for the 82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI.

Configuration of the duplex operation of the Ethernet controller can be forced or determined via the Auto-Negotiation process. See Section 8.6 for details on link configuration setup and resolution.

8.4.1 Full Duplex

All aspects of the IEEE 802.3, 802.3u, 802.3z, and 802.3ab specifications are supported in full duplex operation. Full duplex operation is enabled by several mechanisms depending on the speed configuration of the Ethernet controller and the specific capabilities of the PHY used in the application. During full duplex operation, the Ethernet controller may transmit and receive packets simultaneously across the link interface.

In Internal Serdes mode for the 82546GB/EB and 82545GM/EM (TBI mode for the 82544GC/

EI), the transmission and reception of packets is indicated by symbols embedded in the data stream. These symbols delineate the packet encapsulation and the protocol does not rely on other control signals. See Section 8.2.1.3 for details.

8.4.2 Half Duplex

Note: The Ethernet controller operates in half duplex mode only when configured for internal PHY mode. For the 82546GB/EB and 82545GM/EM, internal SerDes mode does not support half duplex operation.

In half duplex mode, the Ethernet controller attempts to avoid contention with other traffic on the wire, by monitoring the carrier sense signal provided by the internal PHY, and deferring to passing traffic. When the Internal Carrier Sense signal is deasserted or after sufficient InterPacket Gap (IPG) has elapsed after a transmission, frame transmission can begin.

In the case of a collision, the internal PHY asserts a collision signal. Transmission of the frame stops within four clock times and then the Ethernet controller sends a JAM sequence onto the link.

After the end of a collided transmission, the Ethernet controller backs off and attempts to

retransmit per the standard CSMA/CD method. Note that the retransmission is done from the data stored internally in the Ethernet controller transmit packet buffer. The Ethernet controller does not access data in host memory again.

In the case of a successful transmission, the Ethernet controller is ready to transmit any other frames queued in its transmit FIFO within the minimum Inter Frame Spacing (IFS) of the link.

The internal carrier sense signal is expected to be asserted before one slot time has elapsed;

however, the transmission completes successfully even if internal carrier sense is not asserted. If

For receives, the Ethernet controller supports carrier extended packets and packets generated during packet bursting operations (see Section 8.4.2.1 and Section 8.4.2.2). The Ethernet controller can be configured to transmit in packet burst mode via the TCTL.PBE bit in the Transmit Control register (see Section 13.4.46).

Carrier extension is only defined in the IEEE 802.3z standard for half-duplex operation for operation frequencies above 100 Mb/s (Gigabit Ethernet).

8.4.2.1 Carrier Extension (1000 Mb/s Only)

One of the objectives of the IEEE 802.3z standard development was to support a maximum collision domain of 200 m and retain the IEEE 802.3 Ethernet frame format. The scaling of the line transfer rate by 10x to 1 Gb/s reduced the bit time by 10 and effectively reduced the theoretical collision domain to an unusable size with the minimum packet size of 64 bytes. To overcome this, the 802.3z specification development added the notion of carrier extension to the standard.

Carrier extension provides a method to increase the duration of the carrier event to a minimum usable duration in order to meet the collision domain objective. Packets that are signaled from the CSMA/CD layer that do not meet the minimum slot time of 512 bytes have extension bytes appended to them in order to meet this minimum slot time requirement. The extension bytes are defined within the context of the frame encapsulation discussion of the 802.3z standard and are recognized by 802.3z compliant devices (see Figure 8-1).

Figure 8-1. Carrier Extended Frame Format

The Ethernet controller supports the reception and transmission of carrier extended packets. Carrier extension is implemented via specifying the collision distance parameter, COLD, in the Transmit Control register (TCTL). Note that this field is evaluated whether in full- or half- duplex operation.

8.4.2.2 Packet Bursting

In an attempt to recover some of the lost overhead encountered with short duration packets using carrier extension, the IEEE 802.3z standard incorporates the implementation of packet bursting.

Packet bursting is a mechanism that allows a transmitting device to “own-the-wire” for a longer duration and “pack” extra packets in a burst without relinquishing ownership of the medium. A burst length timer is implemented which allows the Ethernet controller to continue to send packets until the timer expires (if packets are available for transmission).

In the case where a transmitting station has more than one packet to send, it can transmit the first packet (extending to 512 bytes if necessary) and then begin the transmission of subsequent packets.

Packet transmission can continue until either there are no more packets ready for transmission, or the burst timer has expired. The burst timer limit is specified as 8 KB.

Duration of Carrier Event Slot Time Minimum Frame Size

Preamble SFD DA SA T/L Data/Pad FCS Extension

The normal rules for IPG are followed during packet bursting after the first packet has met the minimum slot time requirements, with the exception that the Inter Frame Content (IFC) is extension symbols rather than IDLEs. Under some circumstances, it might be desirable to extend this IPG time during a burst. This can be done via the AIFS field in the AIT register. See Section 13.4.35.