Receive and Transmit Description 3
3.2 Packet Reception
3.2.3 Receive Descriptor Format
A receive descriptor is a data structure that contains the receive data buffer address and fields for hardware to store packet information. Table 3-1 lists where the shaded areas indicate fields that are modified by hardware upon packet reception.
Table 3-1. Receive Descriptor (RDESC) Layout
82544GC/EI only
Note: The checksum indicated here is the unadjusted “16 bit ones complement” of the packet. A software assist may be required to back out appropriate information prior to sending it to upper software
•
256 B•
4096 B•
512 B•
8192 B•
1024 B•
16384 B•
2048 B63 48 47 40 39 32 31 16 15 0
0 Buffer Address [63:0]
8 Special Errors Status Packet Checksum
(See Note) Length
63 48 47 40 39 32 31 16 15 0
0 Buffer Address [63:0]
8 Reserved Errors Status Reserved Length
layers. The packet checksum is always reported in the first descriptor (even in the case of multi-descriptor packets).
Upon receipt of a packet for Ethernet controllers, hardware stores the packet data into the indicated buffer and writes the length, Packet Checksum, status, errors, and status fields. Length covers the data written to a receive buffer including CRC bytes (if any). Software must read multiple descriptors to determine the complete length for packets that span multiple receive buffers.
For standard 802.3 packets (non-VLAN) the Packet Checksum is by default computed over the entire packet from the first byte of the DA through the last byte of the CRC, including the Ethernet and IP headers. Software may modify the starting offset for the packet checksum calculation by means of the Receive Control Register. This register is described in Section 13.4.22. To verify the TCP checksum using the Packet Checksum, software must adjust the Packet Checksum value to back out the bytes that are not part of the true TCP Checksum.
3.2.3.1 Receive Descriptor Status Field
Status information indicates whether the descriptor has been used and whether the referenced buffer is the last one for the packet. Refer to Table 3-2 for the layout of the status field. Error status information is shown in Table 3-3.
For multi-descriptor packets, packet status is provided in the final descriptor of the packet (EOP set). If EOP is not set for a descriptor, only the Address, Length, and DD bits are valid.
Table 3-2. Receive Status (RDESC.STATUS) Layout
7 6 5 4 3 2 1 0
PIF IPCS TCPCS RSV VP IXSM EOP DD
Receive Descriptor Status
Bits
Description
PIF (bit 7)
Passed in-exact filter
Hardware supplies the PIF field to expedite software processing of packets.
Software must examine any packet with PIF set to determine whether to accept the packet. If PIF is clear, then the packet is known to be for this station, so software need not look at the packet contents. Packets passing only the Multicast Vector has PIF set.
IP Checksum Calculated on Packet
Note: See Table 3-5 for a description of supported packet types for receive checksum offloading.
Unsupported packet types either have the IXSM bit set, or they don’t have the TCPCS bit set.
3.2.3.2 Receive Descriptor Errors Field
Most error information appears only when the Store Bad Packets bit (RCTL.SBP) is set and a bad packet is received. Refer to Table 3-3 for a definition of the possible errors and their bit positions.
The error bits are valid only when the EOP and DD bits are set in the descriptor status field (RDESC.STATUS)
TCPCS (bit 5)
TCP Checksum Calculated on Packet
When Ignore Checksum Indication is deasserted (IXSM = 0b), TCPCS bit indicates whether the hardware performed the TCP/UDP checksum on the received packet.
0b = Do not perform TCP/UDP checksum; 1b = Perform TCP/UDP checksum Pass/Fail information regarding the checksum is indicated in the error bit (TCPE) of the descriptor receive errors (RDESC.ERRORS).
IPv6 packets may have this bit set if the TCP/UDP packet was recognized.
Reads as 0b.
RSV (bit 4) Reserved Reads as 0b.
VP (bit 3)
Packet is 802.1Q (matched VET)
Indicates whether the incoming packet’s type matches VET (i.e., if the packet is a VLAN (802.1q) type). It is set if the packet type matches VET and CTRL.VME is set. For a further description of 802.1q VLANs, see Chapter 9.
Reads as 0b.
IXSM (bit 2)
Ignore Checksum Indication
When IXSM = 1b, the checksum indication results (IPCS, TCPCS bits) should be ignored.
When IXSM = 0b the IPCS and TCPCS bits indicate whether the hardware performed the IP or TCP/UDP checksum(s) on the received packet. Pass/Fail information regarding the checksum is indicated in the status bits as described below for IPE and TCPE.
Reads as 1b.
EOP (bit 1) End of Packet
EOP indicates whether this is the last descriptor for an incoming packet.
DD (bit 0)
Descriptor Done
Indicates whether hardware is done with the descriptor. When set along with EOP, the received packet is complete in main memory.
Receive Descriptor Status
Bits
Description
Table 3-3. Receive Errors (RDESC.ERRORS) Layout
b. 82541xx, 82547GI/EI, and 82540EP/EM only.
SE
Indicates that a data error occurred during the packet reception. A data error in TBIa mode (82544GC/EI)/internal SerDes (82546GB/EB and 82545GM/EM) refers to the reception of a /V/ code (see Section 8.2.1.3). In GMII or MII mode, the assertion of I_RX_ER during data reception indicates a data error. This bit is valid only when the EOP and DD bits are set; it is not set in descriptors unless RCTL.SBP (Store Bad Packets) control bit is set.
IPE (bit 6)
IP Checksum Error
When set, indicates that IP checksum error is detected in the received packet. Valid only when the IP checksum is performed on the receive packet as indicated via the IPCS bit in the RDESC.STATUS field.
If receive IP checksum offloading is disabled (RXCSUM.IPOFL), the IPE bit is set to 0b. It has no effect on the packet filtering mechanism.
Reads as 0b.
TCPE (bit 5)
TCP/UDP Checksum Error
When set, indicates that TCP/UDP checksum error is detected in the received packet.
Valid only when the TCP/UDP checksum is performed on the receive packet as indicated via TCPCS bit in RDESC.STATUS field.
If receive TCP/UDP checksum offloading is disabled (RXCSUM.TUOFL), the TCPE bit is set to 0b.
It has no effect on the packet filtering mechanism.
Reads as 0b.
CXE RSV (bit 4)
Carrier Extension Error
When set, indicates a packet was received in which the carrier extension error was signaled across the GMII interface. A carrier extension error is signaled by the PHY by the encoding of 1Fh on the receive data inputs while I_RX_ER is asserted.
Valid only while working in 1000 Mb/s half-duplex mode of operation.
3.2.3.3 Receive Descriptor Special Field
Hardware stores additional information in the receive descriptor for 802.1q packets. If the packet type is 802.1q, determined when a packet type field matches the VLAN1 Ethernet Register (VET) and RCTL.VME = 1b, then the special field records the VLAN information and the four byte VLAN information is stripped from the packet data storage. The Ethernet controller stores the Tag Control Information (TCI) of the 802.1q tag in the Special field. Otherwise, the special field contains 0000h.
Table 3-4. Special Descriptor Field Layout 802.1q Packets
All Other Packets
SEQ (bit 2)
Sequence Error
When set, indicates a received packet with a bad delimiter sequence (in TBI mode/
internal SerDes). In other 802.3 implementations, this would be classified as a framing error.
A valid delimiter sequence consists of:
idle start-of-frame (SOF) data, pad (optional) end-of-frame (EOF) fill (optional) idle.
SE (bit 1)
Symbol Error
When set, indicates a packet received with bad symbol. Applicable only in TBI mode/
internal SerDes.
CE (bit 0)
CRC Error or Alignment Error
CRC errors and alignment errors are both indicated via the CE bit. Software may distinguish between these errors by monitoring the respective statistics registers.
a. Not applicable to the 82540EP/EM, 82541xx, or 82547GI/EI.
Receive Descriptor Error
bits
Description
1. Not applicable to the 82541ER.
15 13 12 11 0
12 bits that records the packet VLAN ID number CFI Canonical Form Indicator
1 bit that records the packet’s CFI VLAN field
PRI User Priority
3 bits that records the packet’s user priority field.