PCI Local Bus Interface 4
4.3 PCI/PCI-X Command Usage
The Ethernet controller optimizes the use of PCI/PCI-X bus cycles to maximize throughput. The following sections describe this behavior.
4.3.1 Memory Write Operations
Memory write command usage has been implemented in the Ethernet controller to improve PCI performance. As noted below, cache line size has a significant impact on the usage of memory write commands. Specifically, cache line size entries which are unsupported causes hardware to default to the Memory Write (MW) command for all master write transactions. Also, all writes default to MW if the Memory Write and Invalidate (MWI) enable bit in the PCI configuration command register is 0b. MWI is the preferred write command and is used when the circumstances allow it.
Figure 4-4 depicts a behavioral state-machine representation of the command usage algorithm for master write operations.
Upon EACH master write access, the hardware evaluates the address alignment and the amount of data to be transferred. The following guidelines are used for command determination:
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If the address is cache line aligned and there is at least one cache line of data, then hardware uses the MWI command.•
If the address is aligned but there is not at least one cache line of data, or the address is not aligned, or if the MWI enable bit is set to 0b, then hardware uses the MW command.Figure 4-4. Master Write Command Usage Algorithm
4.3.1.1 MWI Bursts
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If there is at least one cache line of data remaining, then the Ethernet controller continues the MWI burst.•
If there is not at least one cache line of data remaining, then the Ethernet controller terminates the transaction on the boundary, re-acquires the bus, and issues a MW command for the remainder of data.•
If the transaction is terminated prematurely due to a target disconnect or latency time-out, the Ethernet controller re-evaluates command usage based on the new start address and the amount of remaining data. Aligned && (Count >= CLS)Cnt_Rmn = 0
Cnt_Rmn = 0
!MWI_Enable ||
(!Aligned || Cnt_Rmn < CLS) MWI_Enable &&
d && Cnt_Rmn >= CLS)
Cnt_Rmn = Remaining data for XFR CLS = Cache line size
Boundary = At cache line boundary?
Aligned = Address aligned to cache line boundary Count = Amount of data for XFR
Wr_Req || (Cnt_Rmn != 0)
Wr_Req = Initial request for master write
* Either the initiation or continuation of the MWI Burst
Terminate
Terminate = Target disconnect or latency timer ex
4.3.1.2 MW Bursts
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The Ethernet controller always continues the burst until the end. If the system is concerned about MWI usage, it disconnects at the cache line boundary. The Ethernet controller then restarts the transaction and re-evaluates command usage.Note: The algorithm described above defaults to the MW case when the MWI enable bit in the Configuration Register is set to 0b.
4.3.2 Memory Read Operations
For all read commands, the hardware evaluates the amount of data to be read with respect to the cache line size register and the read address alignment for command determination. The following rules apply:
Table 4-8. Rules for Memory Read Operations
In other words, read command usage depends on the number of cache lines from which the data must be read from the target device.
As mentioned above, unsupported values in the cache line size field default to a size of 32 bytes for the memory read command usage algorithm.
Note: MRL should be used for a single cache line of data that is cache line aligned.
4.3.2.1 PCI-X Command Usage
In PCI-X mode, the Ethernet controller takes advantage of split transaction protocol to minimize retries and eliminate delayed read transactions.
Target Split Responses
When the Ethernet controller responds to a Memory Read or I/O Read command it determines if
Amount of Data Requested
Number of Cache Line Boundaries Crossed
Command Used by Hardware
> 2 Cache Lines n/a MRM
>= 1 Cache Line >= 2 MRM
<= 1 Cache Line 0 or 1 MRL
< 1 Cache Line 0 MR
Outstanding Memory Read
When the Ethernet controller masters a memory read and is responded to with a split response it waits for the completion of the data as a target. The Ethernet controller allows one outstanding memory read command at any time. The Ethernet controller continues to master posted memory writes and split completions if there are any.
Relaxed Ordering
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The Ethernet controller takes advantage of the relaxed ordering rules in PCI-X. By setting the RO bit for some of its master transactions, the Ethernet controller allows the system to optimize performance in the following cases:— Relaxed ordering for descriptor and data reads: When the Ethernet controller masters a read transaction its split completion has no relationship with the writes from the CPUs (same direction). It should be allowed to bypass the writes from the CPUs.
— Relaxed ordering for receiving data writes: When the Ethernet controller masters receive data writes it also allows them to bypass each other in the path to system memory because the software does not process this data until their associated descriptor writes are done.
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The Ethernet controller cannot relax ordering for descriptor writes or an MSI write.No Snoop Setting
The Ethernet controller always clears this bit in all of its master transactions because it cannot guarantee that the memory locations between transaction addresses are not cached in the system.