Flexible Substrate

A flexible substrate, such as flexible printed circuit board (fPCB), has an important role in electronic product miniaturization, since their reduced thickness allows them to bend and adapt to various shapes. For example, it has been applied in connecting two rigid substrates or functional modules of consumer handheld devices, mobile devices, and pocket electronic devices. Most flexible substrates are polyimide parylene, Poly Dimethgl Siloxane materials (PDMS), which allow for high-density via traces and tight ball pitches and are thermally advantageous. As one of the most stable organic polymers, polyimide has electric properties the following favorable of a high breakdown voltage over 1 MV/cm and a low relative dielectric constant below 3. In addition, it can be used for Foine-Pitch BGA (FBGA) interposers that closely match the die size in potable electronics. Here is an example of a parylene flexible substrate with microelectrode array for biomicrosystem application.^[43]

Parylene has good biocompatibility (for C-typed parylene), an outstanding moisture bar-rier, excellent chemical inert ness, and extremely high dielectric strength. Additionally, parylene offers good conformability and can be easily patterned by an O2enrolled dry etch-ing process. All of those characteristics make parylene superior to other materials in the applications of flexible microdevices, especially implantable microelectrode arrays (MEAs).

60 Chapter 3 Substrate Technology Recently, microelectrode arrays on a flexible substrate prepared by MEMS technology find diverse applications in neural prostheses, such as restoring hearing to the deaf, vision to the blind, and movement and sensation to the paralyzed. In all these applications, the implanted MEA works as the most important part to bridge the neurons and the outside prosthetic device for transferring the stimulating or recording charges.

A new flexible 3D MEA on parylene substrate has been developed based on the parylene transferring technique. The process can be divided into two parts: the silicon mold process (Part I) and the final parylene 3D MEA process (Part II).

Part I: The silicon mold, which is reusable for the following process, is first fabricated as illustrated in Figure 3.13. A standard 4 inch silicon wafer (Figure 3.13a) was chosen and cleaned in the piranha (H2SO4 and H2O2 solution with a ratio of 4:1 at 120^◦C for 10 min) before the process. A 3 μm-thick photoresist layer was spun onto the wafer and patterned as a mask (Figure 3.13b) for the deep reactive-ion etching (DRIE), in which the 3D cylinder structure with a depth of 100μm and a diameter of 100 μm was formed (Fig.

3.13c). After photoresist removal, an isotropic wet etchant hydrofluoric, nitric, and acetic (HNA) for silicon was applied to shape the cylinders to a tip profile (Fig. 3.13d).

Part I

(a) Standard silicon substrate

(b) Photoresist as DRIE shadow mask

(c) Silicon ICP (Iuductively Coupled Plasma) etching

(d) HNA etching to from the silicon tip array

Figure 3.13 Fabrication process of 3D-tip shaped microelectrodes on a Parylene C substrate.

Part II: After the silicon mold was obtained (Fig. 3.13e), approximately 10 μm parylene C was directly deposited on the structure in a PDS2010 system (Specialty Coating System, Indianapolis, IN, USA; Fig. 3.13f). This parylene deposition process was done at room temperature, and thus hardly introduced any stress into this so-deposited thin parylene

References 61 C film and the silicon mold. The good conformity of parylene C helped it follow the 3D tip profile of the silicon substrate. A dual-layer lift-off technique (Fig. 3.13g) associated with aluminum and AZP4620 was then used to achieve the metallization on this parylene 3D substrate. About 20 nm titanium and 400 nm aluminum were adopted as the first layers to realize undercut for the second photoresist layer, 15 μm-thick AZP4620. This aluminum layer was easily etched off by the aluminum enchant (H3PO4:HAc:HNO3= 16:2:1) for about 20 min with titanium reserved. Subsequently, 20 nm titanium, 150 nm gold, and 50 nm platinum were evaporated onto the substrate. The desired metallization pattern was obtained after bathing the whole structure in the PRS 3000 stripper at 60^◦C for about 2 hours. After the parylene surface was roughened by oxygen plasma etching again, a second parylene C layer about 5 μm was deposited onto the substrate and selectively patterned with lithography followed by the oxygen plasma to expose the stimulating electrodes (Fig.

3.13h). Finally, after removing the left photoresist and Ti/Al, the parylene flexible MEA structure was obtained by carefully peeling off from the substrate (Fig. 3.13i). The final flexible 3D MEA on parylene substrate is shown in Figure 3.14.

Figure 3.14 A 4×5 array of 3D tip-shaped microelectrode on a parylene C substrate

Questions

(1) Why is substrate technology so important in mirosystems packaging?

(2) Analyze the pros and cons of organic PWB substrates and ceramic substrates and in what areas they are used.

(3) Summarize the characteristics of LTCC substrates, major processes of LTCC sub-strates fabrication, and properties of those commonly used metal materials.

References

[1] R.R Tummala. Fundamentals of Microsystems Packaging. New York: McGraw-Hill, 2001.

[2] Zhiyi Weng. Manufacturing technology of multilayer PCB with buried/blind via. Printed Circuit Information, 4 (2004): 8–9 and 20.

[3] Lixin Yao, Wuxue Zhang, and Junli Lian. The Application of AOI system in PCB. Equipment for Electronic Products Manufacturing, 5 (2004): 25–28.

[4] Mingda Shi and Xiaochun Wu. Low cost MCM and its packaging. Applications of IC, 12 (2004): 79–83.

62 Chapter 3 Substrate Technology

[5] Tailun Song. Multi-Chip-Module: the Latest Assembly Technology. Microelectronics, 3 (1995):

1–4.

[6] Minbo Tian. Electronic Package Engineering. Beijing: Tsinghua University Press, 2003.

[7] Zhenyu Han, Jusheng Ma, Zhonghua Xu, et al. Progress of the research on LTCC technology for substrates. Electronic Components and Materials, 6 (2000): 31–34.

[8] Hsu J.Y., Wu N.C., and Yu S.C. Characterization of material for low-temperature sintered multilayer ceramic substrates. Journal of the American Ceramic Society, 10 (1989): 1861.

[9] Jun Wang, Hui Huang, Congxin Li et al. System of Automatic Design of Powdered Metal Forming Process. Computer Aided Engineering, 3 (2000): 20–24.

[10] Anming Li, Yejing Li, Shuhai Wang, et al. Study on the Gel-Casting Technique for 99%

Alumina Substrate. Advanced Ceramics, 4 (2002): 9–13.

[11] Anbing Huang, Song Cui, and Hao Zhang. Technology for directly bonding copper on AIN.

Electronic Components and Materials, 5 (1999): 31–33.

[12] Cui Song, Anbing Huang, and Hao Zhang. Study on Cofired Multiplayer AlN Substrates for MCMs. Electronic Components and Materials, 8 (2003): 25–28.

[13] Yongda Hu, Ming Jiang, Chao Bang, et al. The Study of Aluminum Nitride Co-fire Ceramic Substrate for MEMS Package. Chinese Journal of Scientific Instrument, 3 (2002): 322–323.

[14] Li, G. and Tseng, A.A. Low stress packaging of a micro-machined accelerometer. IEEE Trans-actions on Electronics Packaging Manufacturing, 24.1 (2001): 18–25.

[15] Xintao Zhang, Tao Tang, and Qitu Zhang. Study of Glass-mullite Ceramic Composite Sub-strate. Electronic Components and Materials, 4 (2004): 36–38.

[16] Zhengguo Jin, Nan Lv. Mullite Cerermics in Electricity and Optics. Contributions to Geology and Mineral Resources Research, 4 (1998): 85–89.

[17] Minhua Guo and Tingyue Wang. Soldering of SiC particulate reinforced aluminum(Al/SiC) and low temperature co fired ceramic (LTCC) materials. Materials Science and Technology, s1 (1999): 153–156.

[18] Linjun Wang, Zhijun Fang, and Minglong Zhang. Dielectric and Thermal Properties of Dia-mond Film/Alumina Composite. Journal of Inorganic Materials, 4 (2004): 902–906.

[19] Zhihui Wang. Thick Film Material and Process Applied in Microwave and RF Circuits. Semi-conductor Information, 2 (2000): 21–29.

[20] Shuren Zhang and Yuanjun Zhang. Preparation of the high purity nanometer BeO ceramic powder. Electronic Components and Materials, 6(1999): 1–2.

[21] Zhaowen Dong. Study on the technology for LTCC ceramic substrates. Electronic Components and Materials, 5(1998): 24–28.

[22] Patricia B. Opina, Via filling of green ceramic tape, USP 4802945, 1989-02-07.

[23] T. Williams and A. Shaikh. Silver via metallization of low temperature cofired ceramic tape.

International Symposium on Microelectronics (1994): 324–329.

[24] Shenli Wu. Thin-film Metalization on LTCC Substrates. Electronic Components and Materi-als, 6 (2001): 13–14.

[25] Zhonghua Xu, Zhiting Geng, Zhenyu Han ,et al. History and Research Focus of Low Temper-ature Cofired Ceramics. Materials Review, 4 (2000): 30–33.

[26] M.R. Haskard. Thick-film Hybrids: Manufacture and Design. New York: Prentice Hall, 1988.

[27] Lixi Wan, P. Markondeya Raj, Devarajan Balaraman, et al. Embedded Decoupling Capacitor Performance in High Speed Circuits, 55th Electronic Conponents and Technology Conference,

References 63

Florida, May 31–June 3, 2005.

[28] R. Tuominen, T. Waris and J. Mettovaara. IMB technology for embedded active and passive components in SiP, SiB and single IC package application, ICEP 2009, Kyoto, Japen.

[29] T. Kim, H. Kim, K. Kim, J. Jung, T. Jung, and S. Yi. Tolerance Improvement for Organic Embedded Passive RF Module Substrate, 2008 10th Electronics Packaging Technology Con-ference, Singapore, 1226–1230.

[30] Thelemann T. Thust H and Hintz M. Using LTCC for microsystems. Microelectronics Inter-national, 2002, 19: 19–23

[31] Neubert H. Partsch U. Fleischer D. Gruchow M. Kamusella A. and Pham T.Q., Thick film accelerometers in LTCC-technology-design optimization, fabrication, and characterization. Ac-tuator, 2008, 1–6.

[32] Golonka LJ, Zawada T, Radojewski J, Roguszczak H, and Stefanow MS, LTCC microfluidic system. International Journal of Applied Ceramic Technology, 2006, 3: 150–156.

[33] Ostromecki G, Zawada T, and Golonka LJ. Fluidic micromixer made in LTCC technology-preliminary results. 28th International Spring Seminar on Electronics Technology, 2005, 352–

357.

[34] Golonka LJ, Roguszczak H, Zawada T, Radojewski J, Grabowska I, Chudy M, Dybko A, Brzozka Z, and Stadnik D. LTCC based microfluidic system with optical detection. Sensors and Actuators B, 2005, 111–112: 396–402.

[35] Peterson, KA, Patel KD, Ho CK, Rohde SB, Nordquist CD, Walker CA, Wroblewski BD, and Okandan M. Novel microsystem applications with new techniques in low-temperature co-fired ceramics. International Journal of Applied Ceramic Technology, 2005, 19: 345–363.

[36] Thelemann T, Thust H, Bischoff G, and Kirchne T. Liquid cooled LTCC-substrates for high power applications. International Journal of Microcircuits and Electronic Packaging, 2000, 23:

209–214.

[37] Y.F. Zhang, “Microstructure, Mechanical Behavior and Microchannel Cooling for Low Tem-perature Co-fired Ceramic Substrate,” Thesis for Ph.D. Beijing University, May of 2009.

[38] J. Zhang, Y.F. Zhang, M. Miao, et al. Simulation of fluid flow and heat transfer in microchannel cooling for LTCC electronic packages, to be published in 2009 International Conference on Electronic Packaging Technology, Beijing, China.

[39] N. Mellen, R. Chen, J. Horne, and H. Patterson. WLAN RF Module Design Tradeoffs, 2004 IEEE MTT-S IMS Workshop WSA: Wireless-LAN Solutions and RF Front-End Integration Trends, Fort Worth, June 2004.

[40] J. Liu, Lydia L.W. Leung, et al. Compact and High Efficiency Power Amplifier Module using Integrated Passive Technologies for Wireless LAN Applications. to be published.

[41] Rabindra N. Das, Steven G. Rosser, et al. Resin Coated Copper Capacitive (RC3) Nanocom-posites for Multilayer Embedded Capacitors, 2008 Electronic Components and Technology Conference, 729–735.

[42] M. Sugimura, H. Imai, M. Kawasaki, et al. New Insulation Material with Flat-Surface, Low Coefficient of Thermal Expansion, Low-Dielectric-Loss for Next Generation Semiconductor Packages, 2008 Electronic Components and Technology Conference, 747–752

[43] X.J. Huang. Study on Parylene C-based 3D tip-profile microelectrode array used for retinal prosthesis, MS Dissertation, Beijing University, 2009.

CHAPTER 4

Interconnection Technology

4.1 Introduction

Interconnection technology, the fundamental and exclusive technology for microsystems packaging, is one of four basic technologies in the electronic packaging field. It is one of the research hotspots in the international microelectronics industry.^[1]

Interconnection technology can be used to transfer various physical signals between chips and chips, chips and package, and devices and substrates. Interconnection of electronic signals, the main topic of this chapter, is the most fundamental technology for microsystems packaging technology. Interconnections of optical signals and of fluid signals are discussed in Chapters 2 and 7, respectively.

Braze-welding was the earliest interconnection technique used in electronic engineering.

To meet the requirements for miniaturization in the microelectronics industry, three types of interconnection technologies have been developed and are being widely used. These are wire bonding (WB), tape automated bonding (TAB), and flip chip bonding (FCB).

In the microelectronic packaging field, interconnection technology has a significant in-fluence on the performance of devices. Particularly, the interconnection of chips is crucial to the long-term reliability of electronic components. About one in every three or four malfunctions of IC devices is caused by interconnection failure of chips.

Chips typically cannot be used individually. To exchange information with the outside world, all chips are equipped with I/O interfaces. Only through the interconnection between chips and chips, chips and substrates, and function circuits and systems can the power and signals of chips be allocated and can signals be transmitted. Therefore, the fundamental functions of interconnection are to ensure that chips and devices are correctly connected to the power and ground supplies of a system and to ensure the smooth transmission of signals.

The second function of interconnection is to optimize a wiring structure of packaging. The length of physical wiring is much longer than that of power and signal wiring inside chips, and therefore how the interconnections are performed will have a significant influence on the technical characteristics of all levels of packaging systems. It is essential to define electrical parameters, such as electric resistance, inductance, and capacitance in interconnections used, so as to meet the requirements on the operation of systems.

In addition to electrical functions, some chip-level interconnections can provide mechanical support to the chips or protect the chips and reduce the stress and strain between connected materials by using adhesives. Additionally, a good electric conductor must be a good ther-mal conductor. Often, interconnecting wires (joints) and packaging materials also need to meet the requirements for thermal dissipation when chips are in operation. Therefore, each wire (joint) in the connection of chips acts as an electric conductor, a heat remover and a mechanical support simultaneously.

4.2 Braze-welding Technology

Braze-welding: Braze-welding is a process in which base metals are joined with some melted metals or alloys whose melting points are lower than that of the base metals. The melted metals or alloys will cool down at room temperature to form a strong, sealed joint between the base metals. The melted metals or alloys are called solders.

66 Chapter 4 Interconnection Technology