Chapter 4 Interconnection Technology
4.5 Flip-chip Bonding Technology
encap-sulation and testing.
4. Encapsulation
During chip encapsulation liquid encapsulant is dispensed onto the active face of the chip and cures it, providing the chip protection from moisture. This process is performed after inner wire pressure bonding.
Properties of encapsulant materials to be considered are as follows: solvent resistance, curing procedure, preparation method, mechanical properties, thermal expansion coefficient, ionic contamination level, and final working environment. Epoxy resin, silica gel, polyimide, etc. are common encapsulant materials.
Epoxy resin is the most commonly used encapsulant; it provides ease of operation, similar thermal expansion coefficient to silica gel, low cost, and simple technique, i.e., easy to cure at room temperature or above. It can be applied with an automated dispenser in mass production. Despite its high cost, polyimide is an ideal encapsulant with excellent performance, better than that of epoxy resins.
The encapsulated chips need to be tested, burnt in, and sorted before applying outer wire pressure bonding.
4.4.3 Technical Features
A TAB packaged device has smaller size, lighter weight, and thinner shape. Other features are as follows:
(1) It has good flexibility.
(2) It has high-density input and output counts.
(3) It has excellent electric performance, applicable for high-frequency circuits.
(4) It has high efficiency in thermal management.
(5) It is applicable for automatic assembling. Particularly, inspection and testing can be done automatically to detect defects in early stages.
4.5 Flip-chip Bonding Technology 4.5.1 Basic Concept[13−16]
Flip-chip bonding (FCB) is a process in which bumps are fabricated on a bare chip’s electrode and then interconnected with packaged substrate by using soldering or other tech-niques with the chip’s active face down. This technology replaces interconnection wires with bumps, which are used in traditional wire bonding. The area array I/Os can fit for large-scale and ultra-large-scale integration circuits with the highest assembly density.
FCB was developed in the 1950s–1960s and is now used widely in aviation and avionics, communication, computer science, the automobile industry, and so on. Flipping a chip for interconnection has brought about a series of reformations in microelectronic packaging and has led the direction in high-density packaging. Typical examples include wide applica-tion of BGA, rapid development of CSP, and extensive use of C4 (controlled collapse chip connection) in high-frequency MCM.
Flip-chip bonding has many advantages, such as high precision, small size of hybrid inte-grated chip, high density of I/O, short interconnection wires, and small parasitic parameters.
In flip-chip bonding using reflow soldering, the self-aligned effect can be achieved by using the surface tension of melted filler metals, and thus high precision passive alignment can be realized. Therefore, flip-chip bonding is the first choice for advanced integration of high-density chip/chip interconnection.
74 Chapter 4 Interconnection Technology In addition, in order to achieve high mechanical strength and reliability of devices, the space between chip and substrate can be filled with encapsulants with high thermal con-ductivities. In the past few years, the flip-chip package has gained increasing popularity as the preferred solution for high performance Application Specific Integrated Circuit (ASIC) and microprocessor devices, with a trend toward more I/O, finer pitch, and larger chip size.
In addition, organics substrate has been employed instead of the more expensive ceramic substrate for the cost consideration.[29]
4.5.2 Bonding Process
Flip-chip bonding is composed of bump preparation and flip-chip assembling.
The first step of bump preparation is to prepare the under bump metallization (UBM) on the contact pads of a chip. The functions of UBM are to protect the electrodes on the chip from corrosion and to avoid any other failures, such as cracking and breakage of bump or electrode, caused by incompatibility between bump material and electrode material. The material of the UBM layer is selected based on the materials of the electrode and the bump and the bonding temperature. When the electrode is made of aluminum using the silicon-based Complementary Metal-Oxide-Semiconductor (CMOS) technique, and the bump is Pb-Sn or lead-free, then materials such as Sn-Cu-Ag, Ni, Au, and TiW alloy are used for UBM,[16] as is shown in Figure 4.6.
Bumping is the most complicated step of flip-chip bonding. There are different bumping methods for different bump material. Based on the melting temperature, all the bump materials can be categorized into low—melting point materials, such as lead, tin, indium, and their alloys, and high melting point materials, such as aurum and platinum. Low melting point materials, which are widely used in bump fabrication, have advantages such as low soldering temperature, good plasticity, and CTEs of the two base metals to be bonded that are easy to match. A few examples of bumping methods will be presented in this section.
The combination of photolithography and electroplating or any other metallic film for-mation technique is the most common method, which can form a bump array with high precision, good coherency, tiny spacing, and high density. The method of combining screen printing and reflow soldering can well satisfy the needs for cost reduction, manufacturing process simplification, and large-scale production. In this method, solder paste is placed on a passivated electrode pad via screen printing and then heated to melting temperature. Since the wettability of the pad is better than that of the material around the pad, solder can be converged onto the pad, forming a bump in the ball-coronal shape by surface tension. The size and height of the bump depends on the size of the pad and the amount of the solder paste.
Bump of SnPb or Sn
Nickel Gold
TiW Al SiO2
Figure 4.6 The structure of the bump and passivation layer in flip-chip bonding
4.5 Flip-chip Bonding Technology 75 This method greatly saves cost without the use of expensive facilities, such as photolithog-raphy and electroplating equipment. However, we cannot precisely control the amount of solder pastes, and as a result this method cannot be used in making bump arrays with high precision.
In the flip-chip assembling process, the bumps on chip are bonded to the corresponding metal pads of substrate using a flip-chip bonder. The bumps should be covered with flux before being aligned to the pads. After the alignment, the bumps with a low melting point are reflowed at high temperature and then form solid electrical and mechanical connections at room temperature.
To enhance the reliability of bonding joints, the space between chip and substrate is filled with resin. Typical FOB steps are illustrated in Figure 4.7.
Wafer Bumping Dicing Substrate
Curing Underfill Assembly
Figure 4.7 Typical steps of flip-chip bonding
4.5.3 Main Materials of Flip-chip Bonding[17,18]
1. Chip and Substrate
The interconnection between flip-chip circuits and outside is realized through soldering balls. Generally, aluminum is used in circuit wiring on most of silicon chips. Since aluminum is metallically active, UBM is required. To improve the reliability of solder joints, the UBMs for flip-chip are multilayer metals, which consist of three layers:
(1) Adhesion layer, typical materials are Cr, Ti, V, and W.
(2) Barrier layer, typical materials are Ni, Cu, Pd, and Pt.
(3) Wetting layer, typical materials are gold films, silver films, or gold alloy films.
2. Flux
Flux performs the following functions: (1) Chemically prevents oxidation during the soldering process; (2) Thermally raises the temperature of base metals to be bonded high enough to wet filler metals; (3) Physically improves the wettability of filler metals and covers the entire soldering surface with filler metals.
Additionally, since there’s no solder paste on the substrate, flux will perform the function of the solder paste to adhere to the chip. The amount of flux plays an important role in flip-chip bonding. Too little flux cannot remove oxide on the surface of bumps and clean substrate, while with too much flux, the chip will slide on the substrate and float on flux during reflow soldering, thus producing defects in interconnection. Also, when the bump pitch decreases, the large surface tension of melted solder will attract neighboring bumps, leading to a short circuit. Moreover, too much flux will cause difficulty in back-end cleaning.
3. Underfill
Underfill can reduce thermal mismatching between chip and substrate effectively, improve the reliability of bonding joints, and extend the thermal fatigue life. The lifespan of solder joints is highly dependent on the parameters of underfill.
76 Chapter 4 Interconnection Technology
4.5.4 Reliability of Flip-chip Bonding[3,18]
Many factors could affect the reliability of flip-chip bonding-material, structure, process, etc. Worldwide, the study on the reliability of flip-chip bonding is mainly focused on the following areas.
1. Reliability of Solder Joints[17,19−24]
(1) Shape and height of solder joints and solder composition.
The shapes of solder joint are determined by the wetted area of the interfaces of a chip and substrate, the volume of solder, and the weight of the chip. Generally, a “truncated ball” shaped joint will appear between the bonding interfaces of the chip and the substrate, and the joint height depends on the radius of the wetted area, the volume of the solder, the total number of joints, and the weight of the chip. The height of solder joint refers to the space between the chip and the substrate and is one important factor affecting the reliability in thermal cycling. It has been shown that the fatigue life of a solder joint increases with the increase in the height of the joint. Using the method of stacking solder joints can generate high joints and therefore increase the service lives of solder joints.
The composition of solder ball material has a big influence on the reliability of a solder joint as well. Compared with a Pb-Sn based solder joint, a Pb-In solder joint possesses a better resistance to fatigue. Thermal cycling tests show that adding 15%–20% indium can significantly extend the lifespan of a solder joint. Pure indium solder joints in optoelectronic devices have good reliability.
(2) Analysis of stress and strain of solder joints.
The analysis of the stress and strain of flip-chip solder joints is the basis of the study on the reliability of the solder joints. In the thermal cycling test, strain range results in the accumulation of plastic strain and leads to the failure of solder joints, as a result of the alternating action of creep and fatigue. The analysis of stress and strain of flip-chip solder joints consists of two aspects—the analysis of stress and strain of solder joints in systems with and without underfill.
In a flip-chip bonding system without underfill, the dominant deformation of solder joints is shear deformation, a result of the horizontal displacement of the chip caused by the mismatching of the CTEs between the chip and substrate. The thermal fatigue reliability of solder joints is closely related to their shear strain. On the whole, the shear strain of a solder joint and the distance from the joint to the neutral point (DNP) are in a linear relationship.
Therefore, when the size of a chip increases, the number of solder joints distributed on the edge of the chip will increase, resulting in an increase in the DNP of solder joints. This would affect the thermal fatigue reliability of the system.
Filling underfill in the space between a chip and substrate can relax the CTE mismatching and significantly enhance the thermal fatigue reliability of solder joints.
(3) Life prediction of solder joints.
Life prediction has always been a main topic in thermal fatigue reliability of solder joints.
Strain range and strain energy density are the main failure parameters used in life prediction of solder joints. They can be used to estimate the thermal fatigue life of solder joints.
The failure of solder joints in thermal cycling can be attributed to the initiation and propagation of thermal fatigue cracks. The cumulative damage model–based method of crack initiation and propagation is an important means for assessment of the thermal fatigue reliability of solder joints. There are currently two life prediction methods based on the cumulative damage model. One is a fracture mechanics–based crack growth model, and the other is a cumulative damage–based energy model. The results based on the two models are consistent with experimental results and, therefore, both methods have found applications