System on Chip Technology

8.2.1 Overview

System on chip, usually referred to as SOC or SoC, is a concept that emerged in the 1990s, and whose definition has continuously been enriched with time and technical advancements.

With 65 nm 12 inch wafer manufacturing foundries available, hundreds of million transistors have been integrated in one chip. Currently SOC can be defined as the monolithic integra-tion of a whole set of systems, including basic circuit units, such as one or more processors,

148 Chapter 8 System-level Packaging Technology memories, analog circuitry modules, mixed analog/digital circuit modules, programmable logic units, etc. A schematic of the concept of SOC integration is shown in Figure 8.1. If per-tinent design and process issues can be solved, SOC techniques can provide the availability of system products with the highest integration and weight. Meanwhile, packaging of this chip or microsystem only requires the provision of conventional packaging functions such as signal transmission, power supply, and cooling. Thus the implementation of these kinds of SOC products has been a target pursued by various equipment system and semiconductor vendors.

Figure 8.1 Schematic of the concept of SOC integration

Technologies for SOC include: need to define intellectual property, programmable sys-tem chip, development and application of core chips for IT product, design technology and methodology for SOC, and fabrication technology and process for SOC. From the appli-cation point of view, SOC can be divided into three classes, appliappli-cation specific integrated circuit (ASIC), system on programmable chip (programmable SOC), and original equipment manufacture (OEM) SOC.

With the continuous popularization of SOC applications, the market demands the preva-lence of SOC design. SOC providers must not only expand their design capabilities on the interior of a system, but also directly develop and deliver the SOC design kit and method-ology to their customers. Consequently, SOC design evolves toward programmable SOC.

Programmable SOC is the systematic integration, as required by products, on a field programmable chip. Multiple IC providers have introduced programmable SOC products, the system functions of which include processors, memories, and programmable logic. The most fundamental reason for the popularity of programmable SOCs is that, in addition to the avoidance of the high expense and long fabrication cycle associated with ASICs, they possess high integration with low power, small footprint, low cost of ASICs, and the low risk, flexibility, and quickness of going to market associated with field programmable gate array (FPGA).

8.2.2 SOC Samples

Many SOC products have recently come to market for various applications. Two SOC sam-ples are cited here to give readers an idea of the application. Figure 8.2 shows a SOC sample, MXC6202xG/H/M/N, which integrates MEMS structures sensing dual axis acceleration to-gether with signal processing circuits. Its applications include cell phones, PDAs, computer peripherals, LCD projectors, digital cameras, joysticks, electronic compass tilt corrections, etc. This SOC was fabricated on a standard, submicron complementary metal oxide semicon-ductor (CMOS) process and packaged with a low-profile LCC package in (5× 5 × 1.55)mm³. It is a complete sensor system with on-chip mixed signal processing and integrated I²C bus, allowing the device to be connected directly to a microprocessor, eliminating the need for A/D converters or timing resources. It measures acceleration with a full-scale range of±2g and a sensitivity of 512 counts/g (G/M) or 128 counts/g (H/N) @5.0 V at 25^◦C. It can measure both dynamic acceleration (e.g., vibration) and static acceleration (e.g., gravity).

8.2 System on Chip Technology 149 The device operation is based on heat transfer by natural convection and operates like other accelerometers except that its proof mass is a gas in the MEMSIC sensor.

Figure 8.2 SOC chip integrated MEMS sensing structure IC (Courtesy of MEMSIC, Wuxi, China)

The other SOC sample, as shown in Figure 8.3, is a new generation of controller system for digital TV presented by SMIC Co. Ltd. This CAM controller chip was designed with embedded high-security features. It provides a perfect secure platform for conditional access (CA) application and supports digital content protection on a common interface.

Manufactured by SMIC’s 180 nm standard CMOS process technology, the SOC is em-bedded with ARM7TDMI, and it integrates the common interface, including the transport stream processing unit, the smart card controller, and the DES/3DES/AES/RSA crypto-graph coprocessor. To address security challenges and to provide a security platform for addressing future security needs in CAM, the chip has several hardware blocks embedded to help secure the platform: security OTP block, cryptography coprocessor, memory protec-tion unit (MPU) and secure DMA, encrypted external memory access, and security JTAG interface. It can supply good protection on software and secret information.

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Figure 8.3 Architecture of CAM controller SOC (Courtesy of Shenzhen State Micro Technology Co. Ltd., China)

8.2.3 Problems, Challenges, and Solutions

SOC is the ideal solution for microelectronics products, with its small size, high per-formance, and low cost. People hoped that SOC could evolve in a way similar to that outlined by Moore’s law. However, more and more problems and challenges emerged in the development process, especially those associated with the continuous increase of the types of components needing to be integrated.

The first problem is the compatibility of semiconductor processing. With the enhancement of IC integration, the process of a purely digital IC consists of hundreds of steps. However, a typical SOC chip comprises digital units, analog units, high-voltage units, low-voltage units, radio-frequency units, and even MEMS units. The adoption of each type of unit would significantly increase the complexity and number of steps in the process. Meanwhile, the process compatibility between units of a different type is quite a concern, which embodies itself in a SOC chip with MEMS devices built on.

In general lowering costs and standardizing the process is of great concern, since the MEMS fabrication flow usually comes with specialized process steps like bulk Si etching and Si deep trench etching; the processing temperature sometimes exceeds 400^◦C; and a wide variety of materials are adopted. It is not a surprise that many researchers are trying to make minimal changes to an established standardized process to lower the complexity and cost, or to improve performance by modifing some of the processes for certain kinds of devices.

However, these are not sufficient. The acclaimed advantages of SOC, e.g., minimized volume, ideal performance, and the lowest cost, will not be available at all if no remarkable progress is made on the process to solve the compatibility issue. Concerning the maturity of the solutions to compatibility issues, the majority of SOC products may contain nothing but digital parts, analog parts, and memories.

The second aspect is design complexity. Though both are million-gate-level chips, SOC design is obviously more difficult than that of memory. The complexity is also affected by the

8.2 System on Chip Technology 151 categories of the components integrated, and individual components need to be designed by specialized design engineers so that mask layouts of various portions can be patched together as a whole. When MEMS devices are included in particular, the process design and package design may undergo significant modifications. Meanwhile, if the package design has not been considered along with the circuit and layout design, the development may never be able to be delivered to production. Like the prediction for the of global semiconductor industry, during the first decade of the 21st century, the chip industry is predicted to reach an integration level on the order of billions of transistors, and the mainstream SOC design technologies are incapable of the full integration of a single chip on the 100-million-transistor scale.

The design complexity should be solved in two ways: on the one hand, the continuous advancement of system-level design tools is necessary; on the other hand, IP reuse techniques may be used, i.e., some programmable and general-purpose processing units. These versatile units can be adapted to the needs of various SOC chips, with programming, selection of modules, and setting of parameters. Though this will affect SOC performance to some extent, the compromise is still worthwhile when compared with the development cycle and design cost being saved. In fact, SOC design at present has shown such trends as the constant increase of IP numbers incorporated and the diminishing of the scale of customized modules.

The complexity in design also embodies itself in the design of interconnection between IP core and reusable IP cores. Currently, on-chip bus structures are used to interconnect the IP cores; that is, the cores are not connected directly to each other, rather, they are intercon-nected through on-chip buses. The application of on-chip buses can solve the interconnection issues of IP cores, but, the interconnection between IP cores from different vendors is barely feasible, since different vendors would use bus structures of their own, e.g. AMBA bus for ARM, EC bus for MIPS, and CoreConnect bus for IBM. Therefore, a universal on-chip bus architecture has always been the target sought after by the Virtual Socket Interface Associ-ation (VSIA). For example, an interconnection standard is proposed lately, which is in fact the data traffic between networked IP cores.

Meanwhile, the following challenges have to be faced during the design of a reusable IP core.

(1) Readability. The IP core providers must use designs described with an appropriate method, which can facilitate the use of the IP core for users and can take measures to protect intellectual property from piracy.

(2) The expandability of the design and the applicability of the process flow. An IP core should be carefully designed, verified, and optimized. An IP core needs to be of a certain range of applicability, i.e., to be applicable to a certain range of design and applications.

(3) Testability. IP cores must go through the test and verification. There still may be at least some kind of variation to the IP cores when applied to specific designs. Therefore, the functionality and performance of IP cores should also be tested by customers and should facilitate not only individual tests but also those in system application environments.

(4) The standardization of the interface definition. That is a uniform definition that should be made on the interfaces of IP cores.

(5) Copyright protection.

(6) The intactness of the data delivered to facilitate the integration procedure of chips.

(7) Low power consumption considerations.

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8.3 System in Package Technology