Nano interconnection

Carbon nanotube (CNT) based nanointerconnection technology has been a research in-terest for several years. CNT, if tamed, could be the copper replacement, with the growing

80 Chapter 4 Interconnection Technology awareness that copper is unsuited to future Large Scale Iutegrateod Circuits (LSI) dimen-sions. Fujitsu reported setting a packing density record of 9×10¹¹ CNT/cm², and creating CNT vias of 160 nm in diameter.^[35] The Rensselaer Nanotechnology Center presented a cooling chip through aligned “fins” of CNT. L. Jia et al. from Shanghai Jiao Tong Univer-sity demonstrated a new approach for ultra-fine pitch chip on glass (COG) bonding, called particle on bump (POB) technology.^[36]

COG technology, based on anisotropic conductive films (ACF) for fine pitch flip-chip interconnection, is widely used in flat panel display (FPD) modules for connecting driver ICs to the displays, especially for small size panels, which will be discussed in Chapter 7.

An ACF usually consists of an adhesive epoxy matrix with conductive particles dispersed in it. The conductive particles are metal-coated polymer spheres 3–5 μm in diameter, and the adhesives are thermosetting resins. During the COG bonding process, the conductive particles trapped between the bumps of driver IC and the ITO (Indium Tin Oxide) electrodes of the module panel establish the electrical connections.

As the demand increases for higher resolution and cost reduction, the bump pitch of the driver ICs becomes finer and finer. The current ACF-based COG technology is confronted with two major issues. One is the contact resistance. As the cross-sectional area of the bump decreases with the pitch reduction, the number of the conductive particles trapped between the bumps and the ITO electrodes would decrease. The possibility of having too few particles to fulfill the contact resistance requirement or even forming electrically open joints increases. The other is the short. As the gap between the bumps becomes smaller, the chance of forming electrical shorts due to agglomeration of conductive particles between the adjacent bumps increases. It was demonstrated that the POB process can be implemented in the wafer bumping process. The interconnections formed by POB technique overcome the intrinsic problem with ACF, i.e., conflicting requirements for a large bump contact area to capture enough particles and a large bump gap to avoid shorts with increasingly finer pitch. In the POB technique, the bump size and bump gap are no longer dominated by the conductive particles. Therefore, we can conclude that the POB process is a low-cost viable technique, which has the potential to replace ACF to provide ultra–fine pitch flip-chip on glass solutions for display applications.

Figure 4.10 Schematics particle on bump

(a) particle on bump by intermetallic connection (b) chip on glass by insulated adhesive

Figure 4.10 shows schematically the main process of POB technology. First, one layer of conductive particles is placed on the bump surface of a driver IC with a proper particle den-sity to fulfill the contact resistance requirement, and then, the particles are joined with the bump through intermetallic formation (Figure. 4.10a). Second, the driver IC is assembled on the glass substrate of a liquid crystal display LCD panel with an adhesive by thermal press (Figure. 4.10b).

The key process in POB technology is how to realize the intermetallic connection between the particles and a bump. Since most of the driver ICs in display modules are fabricated with

4.7 Advanced Interconnection 81 the electroplating-Au bumps, and the conductive particles are almost Ni/Au coated polymer spheres, the Au-Sn metallurgy has been adopted to realize the intermetallic connection between particles and bumps. At first, a thin layer of tin was deposited on the top of the Au bumps. Conductive particles 4 μm in diameter with Ni/Au coating on polymer core were manually placed on the tin surface. Then the whole structure was heated in a thermal chamber to the Au-Sn eutectic temperature. In the heating process, the whole annealing time is about 10 minutes.

Figure 4.11 shows those conductive particles trapped under the bumps, which were cap-tured from the backside of the glass substrate by optical microscope. Obviously, there is no agglomeration of conductive particles between the adjacent bumps in the POB image.

This agglomeration is more and more critical to the electrical shorts for the conventional ACF-COG bonding as the bump pitch becomes finer and finer. From the image, we can find that the particles under the bump have a crushed shape similar to the normal ACF-COG particles, which indicates that the particles in both cases provide the same spring effect.^[36]

Figure 4.11 Conductive particles trapped under the bumps for POB-COG bonding

4.7.2 3D Interconnection

Demand for high-speed, high-density, small size, and multifunctional electronic devices has driven the development of 3D packaging, in which different functional devices are expected to integrate into one package.^[37]

3D interconnection for SIP can be classified into five types, including wire bonding for stacked die, vertical interconnecting for package on package (POP), edge interconnection, 3D interconnection for embedded wafer level packaging, and through silicon via (TSV).^[38,39]

The first two approaches are already in mass production, while the rest remain for more investigation.

Wire bonding stacked die is a chip scale package (CSP) that has a small form factor. The traditional wire bonding method is used to connect pads on different dies. Spacers are added in between chips, if there is not enough height for wire bonding.^[40]Wire bonding is a mature technology, with fast bonding speed and low cost. However, long loop wires have large resistance and other parasitic effects that prevent them from attaining high performance usage. In addition, heat dissipation is another problem for wire bonding. Thus, wire bonding technology is usually used to stack memory chips, including flash memory, DRAM (Dynamic Random Access Memory), and some other type memories. T. Watanabe presents a recent

82 Chapter 4 Interconnection Technology wire bonding stacked die result that DRAM chips are stacked together, with wires of a rather high density.^[41]

In order to solve the reliability problem, a modified POP using through mold via (TMV) as the bottom module comes out.^[42] TMV has a full molded bottom module with vias providing electrical interconnect. As a result, the bottom module has a closer warpage curve with the top module, which can reduce the total warpage. Figure 4.12 shows a sketch of POP with the TMV bottom module.

Figure 4.12 Sketch of POP with TMV bottom module

Edge interconnection is an emerging technology. Conductive adhesive is used to connect each die stacked together. A needle with conductive adhesive on its tip moves along a triangle path to extrude conductive adhesive between pads of different chips. The advantage of edge interconnection is that it can provide shorter interconnection and is supposed to be low cost. In addition, it can be stacked up as high as 128 dies.^[38]However, edge interconnection can only be used in chips with the same size, such as memory chips. An example of edge interconnection was presented by Vertical Circuits.^[43]

Through silicon via is believed to be the best 3D die stacking method.^[44] TSV has the shortest interconnection distance, which means it has the fastest speed. Besides application in memory chip stacking, TSV can also be used for heterogeneous integration, in which logic, memory, MEMS, optical, and RF are stacked together. With embedded microfluidic channels, TSV can also solve heat dissipation problems. Figure 4.13 shows a sketch of dies stacked up with TSV.

TSV fabrication process includes “via first” and “via last” approaches. Via first means fabrication TSV before CMOS process, while the via last approach means fabricating TSV right after the CMOS process, and before the packaging process. The via first approach usually forms small vias, about 5μm or less. Polysilicon or tungsten is used to fill these vias, providing electrical connection from the front side to the back side. The via last approach usually focuses on larger TSVs, from 10μm to 100 μm in diameter. Electrical plating copper is widely used to fill these large TSVs, for its low resistance, high throughput, and low cost.

The CMOS image sensor (CIS) is the first commercial product using TSV technology. A CIS with TSVs can be directly mounted on the PCB of a consumer mobile product through the back side electric contact, which greatly reduces its size.^[45] Figure 4.14 shows a sketch of the CIS module with TSV.

IC, MEMS, RF, passive, biochip, etc.

Figure 4.13 Sketch of TSV stacked dies Figure 4.14 Sketch of CIS with TSV

References 83

Questions

(1) What are the characteristics of WB, FC, and TAB interconnections? In what areas are they mainly used?

(2) What are the characteristics of 3D interconnection? What do the main methods for 3D interconnection include?

(3) What parameters should be taken into account when choosing solder? Why should we develop lead-free solder?

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CHAPTER 5

Device-level Packaging

5.1 Introduction 5.1.1 Basic Concepts

Device-level package (DLP), also called single chip package, encapsulates a single circuit or chip to provide it with the necessary electronic connections, mechanical support, thermal management, protection from harmful elements, and an interface for future applications.

Packaging for two or more chips in a single module is usually called multichip package or multichip module.

A typical process of device level packaging is shown in Figure 5.1, including dicing, mount-ing, bondmount-ing, encapsulatmount-ing, markmount-ing, leads or solder ball fabrication, and unification of the finished product.

(a) Dicing

IC chip

(b) Mounting

(c) Bonding (d) Encapsulation

(e) Testing

Figure 5.1 Typical process of device-level packaging

5.1.2 Status and Role

As a very important part of microsystem package technology, DLP guarantees a normal chip proper operation and communication between the chip and the environment. There are many kinds of DLPs, all of which should have the following basic features:

(1) Provide a reliable electronic signal I/O transmission to provide power, grounding, signals, and other stable and reliable power supply.

88 Chapter 5 Device-level Packaging